Preserving the seed layer on sti edge and improving the epitaxial growth

Patent metadata

Field	Value
Publication number	US-2016343607-A1
Application number	US-201514716938-A
Country	US
Kind code	A1
Filing date	May 20, 2015
Priority date	May 20, 2015
Publication date	Nov 24, 2016
Grant date	—

Abstract

A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.

First claim

What is claimed is:

1 . A method comprising:
forming a shallow trench isolation (STI) etch mask over a silicon (Si) substrate, the STI etch mask having laterally separated openings on opposite sides of the Si substrate; forming shallow trenches in a portion of the Si substrate through the openings; forming first, second, third, and fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down through a portion of the Si substrate; forming a STI oxide layer over the first, second, third, and fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.

2 . The method according to claim 1 , comprising forming the STI etch mask of nitride.

3 . The method according to claim 1 , comprising forming the STI etch mask to a thickness of 10 nanometer (nm) to 100 nm.

4 . The method according to claim 1 , comprising forming the openings with a width of 20 nm to 200 nm.

5 . The method according to claim 1 , comprising forming the first, second, third, and fourth oxide spacers by:
forming an oxide layer along the sidewalls of the shallow trenches; and etching the oxide layer down to the Si substrate along a pair of opposite sidewalls.

6 . The method according to claim 1 , comprising forming each of the first, second, third, and fourth oxide spacers with a width of 5 nm to 100 nm.

7 . The method according to claim 1 , comprising forming the deep STI trenches by:
removing the STI etch mask except adjacent to the first oxide spacer, but opposite the second oxide spacer; between the second and third oxide spacers; and adjacent to the fourth oxide spacer, but opposite the third oxide spacer, the portion of the STI etch mask remaining; etching the substrate between the first and second oxide spacers and between the third and fourth oxide spacers to a depth of 100 nm to 500 nm; and etching opposite sidewalls of the deep STI trenches at a 70° to 90° angle.

8 . A method comprising:
forming shallow trench isolation (STI) structures in a silicon (Si) substrate, the STI structures laterally separated; forming a spacer material layer over each STI structure and extending over a portion of the Si substrate; forming a gate structure on the Si substrate equidistant between the spacer material layers; forming a photoresist over each of the spacer material layers; forming a first cavity in the Si substrate between each spacer material layer and the gate structure, the first cavity formed under an equal portion of the spacer material layer and the gate structure; forming a second cavity in the Si substrate through the first cavity, the second cavity formed under an equal portion of the spacer material layer and the gate structure; and forming an epitaxial layer in the second cavity, the epitaxial layer formed higher than the spacer.

9 . The method according to claim 8 , comprising forming the spacer material layer of nitride.

10 . The method according to claim 8 , comprising forming the spacer to a thickness of 3 nanometer (nm) to 30 nm.

11 . The method according to claim 8 , comprising forming the spacer material layer extending 5 nm to 50 nm over the portion of the Si substrate.

12 . The method according to claim 8 , comprising forming the first and second cavities as box-shaped cavities.

13 . The method according to claim 8 , comprising forming the first cavity in the Si substrate to a depth of 5 nm to 50 nm.

14 . The method according to claim 8 , comprising forming the first cavity by:
dry etching.

15 . The method according to claim 8 , comprising forming the second cavity by:
wet etching.

16 . A transistor device comprising:
a silicon (Si) substrate; a gate structure formed on the Si substrate; shallow trench isolation (STI) structures formed in the Si substrate on opposite sides of the gate structure; seed layer protection structures formed over the Si substrate on opposite sides of the gate structure; and epitaxial structures formed in the Si substrate under the seed protection structure and the gate structure, the epitaxial structures formed on opposite sides of the gate structure.

17 . The device according to claim 16 , wherein the seed protection structure is formed as part of the STI structure.

18 . The device according to claim 16 , wherein the seed protection structure is formed as a nitride spacer material layer over the STI structure and extending over a portion of the Si substrate.

19 . The device according to claim 16 , wherein the epitaxial structure is formed in a box-shaped, sigma-shaped, or ball-shaped cavity in the Si substrate.

20 . The device according to claim 16 , wherein the epitaxial structure is formed higher than the seed protection structure.

Assignees

• Globalfoundries Inc

Inventors

• Wan Jing
• Chen Jer-Hueih(James)
• Xu Cuiqin
• Nagaiah Padmaja

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title