Textured Silicon Liners In Substrate Processing Systems

Patent metadata

Field	Value
Publication number	US-2016343545-A1
Application number	US-201615227298-A
Country	US
Kind code	A1
Filing date	Aug 3, 2016
Priority date	Jun 27, 2013
Publication date	Nov 24, 2016
Grant date	—

Abstract

Substrate processing systems, such as ion implantation systems, deposition systems and etch systems, having textured silicon liners are disclosed. The silicon liners are textured using a chemical treatment that produces small features, referred to as micropyramids, which may be less than 20 micrometers in height. Despite the fact that these micropyramids are much smaller than the textured features commonly found in graphite liners, the textured silicon is able to hold deposited coatings and resist flaking. Methods for performing preventative maintenance on these substrate processing systems are also disclosed.

First claim

What is claimed is:

1 . A substrate processing system, comprising:
a process chamber, having a plurality of chamber walls, in which said substrate is disposed; a feed gas source in communication with said process chamber; a plasma generator to create a plasma from said feed gas; and a silicon liner disposed on a surface of at least one of said chamber walls of said process chamber, wherein a surface of said silicon liner facing an interior of said process chamber is textured.

2 . The substrate processing system of claim 1 , wherein said textured surface of said silicon liner comprises micropyramids having a height of less than 20 micrometers.

3 . The substrate processing system of claim 2 , wherein said micropyramids vary in height.

4 . The substrate processing system of claim 2 , wherein spacing between said micropyramids varies.

5 . The substrate processing system of claim 1 , wherein said textured surface of said silicon liner comprises a chemically treated surface.

6 . The substrate processing system of claim 1 , wherein the silicon liner is textured by treating the surface with a hydroxide.

7 . The substrate processing system of claim 6 , wherein the hydroxide is one of sodium hydroxide or barium hydroxide.

8 . The substrate processing system of claim 1 , wherein said at least one of the chamber walls is electrically biased and said silicon liner is doped so as to reduce its bulk resistivity.

9 . A substrate processing system, comprising:
a process chamber, having a plurality of chamber walls, in which said substrate is disposed; a feed gas source in communication with said process chamber; an electrically biased target disposed in the process chamber; and a silicon liner disposed on a surface of at least one of said chamber walls of said process chamber, wherein a surface of said silicon liner facing an interior of said process chamber is textured.

10 . The substrate processing system of claim 9 , wherein said textured surface of said silicon liner comprises micropyramids having a height of less than 20 micrometers.

11 . The substrate processing system of claim 10 , wherein said micropyramids vary in height.

12 . The substrate processing system of claim 10 , wherein spacing between said micropyramids varies.

13 . The substrate processing system of claim 9 , wherein said textured surface of said silicon liner comprises a chemically treated surface.

14 . The substrate processing system of claim 9 , wherein the silicon liner is textured by treating the surface with a hydroxide.

15 . The substrate processing system of claim 14 , wherein the hydroxide is one of sodium hydroxide or barium hydroxide.

16 . The substrate processing system of claim 9 , wherein said at least one of the chamber walls is electrically biased and said silicon liner is doped so as to reduce its bulk resistivity.

Assignees

• Varian Semiconductor Equipment Ass Inc

Inventors

• Blake Julian

Classifications

• H01J2237/022

  Avoiding or removing foreign or contaminating particles, debris or deposits on sample or tube · CPC title

• H01J2237/334

  Etching · CPC title

• H01J37/32477

  characterised by the means for protecting vessels or internal parts, e.g. coatings · CPC title

• H01J37/3171 Primary

  for ion implantation · CPC title

• C23C14/564

  Means for minimising impurities in the coating chamber such as dust, moisture, residual gases · CPC title