Real-time cache behavior forecast using hypothetical cache

Patent metadata

Field	Value
Publication number	US-2016342518-A1
Application number	US-201514716077-A
Country	US
Kind code	A1
Filing date	May 19, 2015
Priority date	May 19, 2015
Publication date	Nov 24, 2016
Grant date	—

Abstract

Systems and methods for forecasting behavior of caches include a hypothetical cache. The hypothetical cache is configured to emulate cache behavior, and performance metrics for the hypothetical cache are determined, where the performance metrics may be based on cache hits/misses. Performance metrics for a real cache of a processor core of a processing system may also be similarly determined Behavior of the real cache is forecast based, at least, on performance metrics of the hypothetical cache, and in some cases, also on performance metrics of the real cache (e.g., based on a comparison of the performance metrics). Actions may be recommended and/or performed based on the forecast, where the actions include modifying the real cache size, associativity, or allocation for processor cores, migrating a task running in one processor cluster to another processor cluster, or for collecting data for the real cache for offline analysis.

First claim

What is claimed is:

1 . A processing system comprising:
a processor core; a real cache of the processor core; a hypothetical cache to emulate cache behavior; and an optimization module to forecast behavior of the real cache based, at least, on performance metrics of the hypothetical cache.

2 . The processing system of claim 1 , wherein forecasted behavior of the real cache comprises a prediction of performance metrics of the real cache based on one or more modifications of characteristics of the real cache.

3 . The processing system of claim 1 , wherein the optimization module is further configured to, based on the forecasted behavior, recommend one or more actions to:
dynamically modify a size of the real cache; dynamically modify allocation of the real cache to the processor core; migrate a task running on the processor core to another processor core; dynamically modify associativity of the real cache; or collect data for the real cache.

4 . The processing system of claim 1 further configured to perform one or more actions recommended by the optimization module.

5 . The processing system of claim 1 , comprising:
a real cache miss counter to provide performance metrics for the real cache; and a hypothetical cache miss counter to provide performance metrics for the hypothetical cache.

6 . The processing system of claim 5 , further comprising:
a comparison module to compare performance metrics of the real cache and performance metrics of the hypothetical cache, wherein the optimization module is further configured to forecast behavior of the real cache based on the comparison.

7 . The processing system of claim 1 , wherein
the real cache and the processor core belong to a first processor cluster and the hypothetical cache is an idle cache of a second processor cluster.

8 . The processing system off claim 7 , wherein the second processor cluster comprises one or more processing cores which are idle or powered down.

9 . The processing system of claim 8 , configured to migrate a task running on the processor core of the first processor cluster to the second processor cluster based on the forecasted behavior of the real cache.

10 . The processing system of claim 1 , wherein the hypothetical cache is a cache shell, wherein the cache shell comprises a tag structure and logic to provide performance metrics for the hypothetical cache, and wherein the cache shell does not comprise data.

11 . The processing system of claim 10 , wherein the hypothetical cache comprises:
a translation look-aside buffer (TLB) and corresponding time stamps to indicate times at which pages hitting in the TLB are accessed for a task; and a page table and corresponding time stamps to indicate times at which pages missing in the TLB are accessed for the task.

12 . The processing system of claim 11 , comprising logic to filter out pages with time stamps older than a predetermined time point to provide a number of active pages for the task.

13 . The processing system of claim 12 , further comprising a multiplier to multiply the number of active pages with a page size of each page to determine a memory requirement for the task.

14 . The processing system of claim 13 , wherein the optimization module is further configured to forecast an upper bound for a size of the real cache based on the memory requirement.

15 . The processing system of claim 1 , wherein the real cache is a Level 2 (L2) cache of the processor core and the hypothetical cache is configured as a Level 3 (L3) cache of the processor core.

16 . The processing system of claim 15 , wherein the optimization module is configured to recommend an action to increase the size of the real cache, based on the forecasted behavior, if a product of a miss rate of the real cache and a hit rate of the hypothetical cache is greater than a predetermined threshold.

17 . The processing system of claim 16 , further comprising a hypothetical cache emulation module configured to sample transactions from the processor core, at a sampling interval which is selected from a random sequence, a pseudorandom sequence, or regular interval, based on a sampling algorithm, or adjustable based on a clock frequency of the hypothetical cache.

18 . A method of forecasting behavior of a real cache of a processor core, the method comprising:
emulating cache behavior with a hypothetical cache; determining performance metrics of the hypothetical cache; and forecasting behavior of the real cache based, at least, on the performance metrics of the hypothetical cache.

19 . The method of claim 18 , further comprising recommending one or more actions based on forecasting behavior of the real cache, the one or more actions comprising:
dynamically modifying a size of the real cache; dynamically modifying allocation of the real cache to the processor core; migrating a task running on the processor core to another processor core; dynamically modifying associativity of the real cache; or collecting data for the real cache.

20 . The method of claim 18 , further comprising:
determining performance metrics for the real cache.

21 . The method of claim 20 , further comprising:
forecasting behavior of the real cache based on a comparison of the performance metrics of the real cache and performance metrics of the hypothetical cache.

22 . The method of claim 18 , comprising configuring an idle cache as the hypothetical cache, wherein the real cache and the processor core belong to a first processor cluster and the idle cache belongs to a second processor cluster.

23 . The method of claim 22 , further comprising migrate a task running on the processor core of the first processor cluster to the second processor cluster based on the forecasted behavior of the real cache.

24 . The method of claim 18 , comprising configuring the hypothetical cache as a cache shell, wherein the cache shell comprises a tag structure and logic to provide performance metrics for the hypothetical cache, and wherein the cache shell does not comprise data.

25 . The method of claim 18 , comprising configuring the hypothetical cache with a
a translation look-aside buffer (TLB) and corresponding time stamps to indicate times at which pages hitting in the TLB are accessed for a task; and a page table and corresponding time stamps to indicate times at which pages missing in the TLB are accessed for the task.

26 . The method of claim 25 , further comprising filtering out pages with time stamps older than a predetermined time point to provide a number of active pages for the task, and multiplying the number of active pages with a page size of each page to determine a memory requirement for the task.

27 . The method of claim 26 , further comprising forecasting an upper bound for a size of the real cache based on the memory requirement.

28 . The method of claim 18 , comprising configuring the real cache as a Level 2 (L2) cache of the processor core and the hypothetical cache as a Level 3 (L3) cache of the processor core and forecasting benefits of increase the size of the real cache, based on comparison of a product of a miss rate of the real cache and a hit rate of the hypothetical cache with a predetermined threshold.

29 . The method of claim 18 , further comprising sampling transactions from the processor c

Assignees

• Qualcomm Inc

Inventors

• Park Hee Jun
• Rychlik Bohuslav
• Thomson Steven S

Classifications

• G06F2212/283

  Plural cache memories · CPC title

• G06F2212/6032

  Way prediction in set-associative cache · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/684

  TLB miss handling · CPC title

• G06F12/0864 Primary

  using pseudo-associative means, e.g. set-associative or hashing · CPC title