Framework for forming electronic display from plurality of electronic devices

US2016342373A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016342373-A1
Application numberUS-201514789187-A
CountryUS
Kind codeA1
Filing dateJul 1, 2015
Priority dateMay 19, 2015
Publication dateNov 24, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A framework for forming an electronic display includes a primary electronic device, at least one coupling electronic device, and at least one secondary electronic device. The primary electronic device includes a system on a chip electronically coupled to a display screen of the primary electronic device. The at least one coupling electronic and the at least one secondary electronic device each includes an integrated circuit and a corresponding display screen. Each electronic device includes at least one connector configured to electronically couple to the connector of another electronic device. The system on a chip of the primary electronic device controls the display screen of each of the electronic devices to display a portion of the electronic display.

First claim

Opening claim text (preview).

What is claimed is: 1 . A framework for forming a composite electronic display, the framework comprising: a first electronic device comprising a first display screen; and a second electronic device comprising a second display screen; wherein the first display screen and the second display screen cooperatively form an electronic display when the second electronic device is electronically coupled to the first electronic device. 2 . The framework as in claim 1 , wherein: the first electronic device comprises a first connector; the second electronic device comprises a second connector; and the second electronic device is electronically coupled to the first electronic device by the second connector electronically coupling to the first connector. 3 . The framework as in claim 2 , wherein: the first electronic device further comprises a system on a chip electronically coupled to the first display screen and comprises a control module; the second electronic device comprises an integrated circuit electronically coupled to the second display screen; the control module transmits a high-level voltage signal to the system on a chip when the second electronic device is electronically coupled to the first electronic device; and when the system on a chip receives the high-level voltage signal from the control module, the system on a chip controls the first display screen to display a first portion of an electronic display, and controls the second display screen to display a second portion of the electronic display. 4 . The framework as in claim 3 , wherein: the system on a chip comprises an enabling pin and a first transmission pin; the control module comprises an electronic switch, a first resistor, and a second resistor; the electronic switch is configured to transmit the high-level voltage signal to the system on a chip; the electronic switch comprises a first terminal, a second terminal, and a third terminal; the first connector comprises a detection pin and a second transmission pin; the second connector comprises a ground pin and a third transmission pin; the first transmission pin is electronically coupled to the second transmission pin, and the third transmission pin is electronically coupled to the integrated circuit; the first terminal of the electronic switch is electronically coupled to a power source through the first resistor of the control module, and also electronically coupled to the detection pin of the first connector; the second terminal of the electronic switch is electronically coupled to a power source through the second resistor of the control module, and also electronically coupled to the enabling pin of the system on a chip; the third terminal of the electronic switch is electronically coupled to ground; when the second connector is electronically coupled to the first connector, the detection pin and the second transmission pin of the first connector are electronically coupled to the ground pin and the third transmission pin of the second connector, respectively; the detection pin electronically coupled to the ground pin transmits a low-level voltage signal to the electronic switch, thereby closing the electronic switch; the closed electronic switch transmits the high-level voltage signal to the enabling pin of the system on a chip; the first transmission pin, upon the enabling pin receiving the high-level voltage signal, transmits data to the integrated circuit of the second electronic device through the second transmission pin and the third transmission pin; and upon the integrated circuit receiving the data from the first transmission pin, the system on a chip controls the second display screen through the integrated circuit to display the second portion of the electronic display. 5 . A framework for forming an electronic display, the framework comprising: a first electronic device comprising a first display screen and a system on a chip electronically coupled to the first display screen; a second electronic device comprising a second display screen and a first integrated circuit electronically coupled to the second display screen; and a third electronic device comprising a third display screen and a third integrated circuit electronically coupled to the third display screen; wherein the first, second, and third display screens cooperatively form an electronic display when the first, second, and third electronic devices are electronically coupled together. 6 . The framework as in claim 5 , wherein: the first electronic device comprises a first connector; the second electronic device comprises a second connector and a third connector; the third electronic device comprises a fourth connector; the first electronic device is electronically coupled to the second electronic device by the first connector electronically coupling to the second connector; and the second electronic device is electronically coupled to the third electronic device by the third connector electronically coupling to the fourth connector. 7 . The framework as in claim 6 , wherein: the first electronic device comprises a first control module; the second electronic device comprises a second control module; the first control module transmits a high-level voltage signal to the system on a chip when the second electronic device is electronically coupled to the first electronic device; the second control module transmits a high-level voltage signal to the system on a chip when the third electronic device is electronically coupled to the second electronic device; and when the system on a chip receives the high-level voltage signal from the first control module and the second control module, the system on a chip controls the first display screen to display a first portion of an electronic display, the second display screen to display a second portion of the electronic display, and the third display screen to display a third portion of the electronic display. 8 . The framework as in claim 7 , wherein: the system on a chip comprises a first enabling pin, a second enabling pin, a first transmission pin, and a second transmission pin; the first control module comprises a first electronic switch, a first resistor, and a second resistor; the first electronic switch is configured to transmit the high-level voltage signal to the system on a chip; the first electronic switch comprises a first terminal, a second terminal, and a third terminal; the first connector comprises a first detection pin, a third transmission pin, a fourth transmission pin, and a fifth transmission pin; the second connector comprises a first ground pin, a sixth transmission pin, a seventh transmission pin, and an eighth transmission pin; the sixth transmission pin and the first ground pin are electronically coupled to the first integrated circuit and to ground, respectively; the second control module comprises a second electronic switch, a third resistor, and a fourth resistor; the second control module is configured to transmit the high-level voltage signal to the system on a chip; the second electronic switch comprises a first terminal, a second terminal, and a third terminal; the third connector comprises a ninth transmission pin and a second detection pin; the fourth connector comprises a tenth transmission pin and a second ground pin; the first transmission pin and the first enabling pin are electronically coupled to the third transmission pin and the first detection pin, respectively, through the first control module; the second transmission pin and the second enabling pin are electronically coupled to the fourth transmission pin and the fifth transmission pin; the first terminal of the first electronic switch is electronic

Assignees

Inventors

Classifications

  • Detection of presence or absence of input display information or of connection or disconnection of a corresponding information source · CPC title

  • G06F3/1446Primary

    display composed of modules, e.g. video walls · CPC title

  • Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions · CPC title

  • Electrical details of casings, e.g. terminals, passages for cables or wiring · CPC title

  • with operator interface units · CPC title

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What does patent US2016342373A1 cover?
A framework for forming an electronic display includes a primary electronic device, at least one coupling electronic device, and at least one secondary electronic device. The primary electronic device includes a system on a chip electronically coupled to a display screen of the primary electronic device. The at least one coupling electronic and the at least one secondary electronic device each …
Who is the assignee on this patent?
Hong Fu Jin Prec Ind (Wuhan) Co Ltd, Hon Hai Prec Ind Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/1446. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Nov 24 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).