Chip structure

Patent metadata

Field	Value
Publication number	US-2016340180-A1
Application number	US-201514718152-A
Country	US
Kind code	A1
Filing date	May 21, 2015
Priority date	May 21, 2015
Publication date	Nov 24, 2016
Grant date	—

Abstract

One example discloses an chip, comprising: a substrate; a first side of a passivation layer coupled to the substrate; a device, having a device height and a cavity, wherein a first device surface is coupled to a second side of the passivation layer which is opposite to the first side of the passivation layer; and a set of structures coupled to the second side of the passivation layer and configured to have a structure height greater than or equal to the device height.

First claim

1 . A chip, comprising:
a substrate; a first side of a passivation layer coupled to the substrate; a device, having a device height and a cavity, wherein a first device surface is coupled to a second side of the passivation layer which is opposite to the first side of the passivation layer; and a set of structures coupled to the chip, the set of structures configured to have a structure height greater than or equal to the device height and configured to reduce at least one of pressure gradients or damage to the device during processing of the chip.

2 . The chip of claim 1 , wherein the set of structures are coupled to the substrate.

3 . The chip of claim 1 wherein the set of structures are coupled to the second side of the passivation layer.

4 . The chip of claim 1 , wherein the structures are of a same type and are on at least four sides of the device.

5 . The chip of claim 4 , wherein the structure types include at least one of: a rigid structure, a closed device, a spacer structure, a support structure, a reference capacitor, a decoupling capacitor, a polyimide, or a structure that does not contain a cavity.

6 . The chip of claim 1 , wherein the structures completely surround the device.

7 . The chip of claim 1 , wherein the set of structures are configured to have a structure height greater than or equal to the device height.

8 . The chip of claim 1 , wherein the set of structures include a surface configured to receive an adhesive tape.

9 . The chip of claim 8 , further comprising the adhesive tape, wherein the tape is coupled only to the structures.

10 . The chip of claim 1 , wherein the device is at least one of: a membrane, a transducer, a MEMS device, or a pressure sensor.

11 . The chip of claim 1 , further comprising a seal layer on top of the device.

12 . The chip of claim 1 , wherein the substrate includes an integrated circuit on the first side of the passivation layer.

13 . The chip of claim 12 , wherein the integrated circuit is an analog circuit and the structures are decoupling capacitors.

14 . The chip of claim 12 , wherein the integrated circuit does not include the structures.

15 . A method fabricating a chip, wherein the chip comprises:
a substrate; a first side of a passivation layer coupled to the substrate; a device, having a device height and a cavity, wherein a first device surface is coupled to a second side of the passivation layer which is opposite to the first side of the passivation layer; and a set of structures coupled to the second side of the passivation layer and configured to have a structure height greater than or equal to the device height, the method comprising:
applying tape to a first side of the chip;
grinding a second side of the chip opposite to the first side; and
wherein the structures are configured to spread a pressure exerted during the grinding process so as to reduce at least one of pressure gradients or damage to the device during the grinding process.

16 . The method of claim 15 , further comprising removing the tape from the chip, wherein the structures are configured to prevent removal of the tape from damaging the device.

Assignees

• Ams Int Ag

Inventors

• Daamen Roel
• Bouman Hendrik
• Vijayakumar Kailash

Classifications

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• B81B2201/0264

  Pressure sensors · CPC title