System and Method for Hybrid Photonic Electronic Switching

Patent metadata

Field	Value
Publication number	US-2016337723-A1
Application number	US-201514711098-A
Country	US
Kind code	A1
Filing date	May 13, 2015
Priority date	May 13, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

A method includes comparing a length of a first packet to a threshold, determining that the first packet is a short packet when the length of the first packet is less than the threshold, and determining that the first packet is a long packet when the length of the first packet is greater than or equal to the threshold. The method also includes when the first packet is a long packet placing the first packet in a long packet container and transmitting the long packet container to a photonic switch. Additionally, the method includes when the first packet is a short packet placing a first portion of the first packet in a first short packet container, where the first short packet container includes a sequence number, a source top-of-rack switch (TOR) address, and a destination TOR address and transmitting the first short packet container to an electronic switch.

First claim

What is claimed is:

1 . A method comprising:
comparing a length of a first packet to a threshold; determining that the first packet is a short packet when the length of the first packet is less than the threshold; determining that the first packet is a long packet when the length of the first packet is greater than or equal to the threshold; when the first packet is a long packet:
placing the first packet in a long packet container; and
transmitting the long packet container to a photonic switch; and
when the first packet is a short packet:
placing a first portion of the first packet in a first short packet container, wherein the first short packet container comprises
a sequence number,
a source top-of-rack switch (TOR) address, and
a destination TOR address; and

transmitting the first short packet container to an electronic switch.

2 . The method of claim 1 , wherein the short packet container further comprises:
a concatenation sequence length number (CSL); and a basic payload container (BPC) position in sequence (BPS) number.

3 . The method of claim 1 , wherein the first portion of the first packet is an entirety of the first packet.

4 . The method of claim 1 , further comprising:
placing a second portion of the first packet in a second short packet container; and transmitting the second short packet container to the electronic switch.

5 . The method of claim 4 , wherein the first short packet container has a first header, wherein the first header has a first header size, wherein the second short packet container has a second header, wherein the second header has a second header size, and wherein the first header size is larger than the second header size.

6 . The method of claim 4 , wherein the second packet container comprises a first trailer, and wherein the first packet container does not have a trailer.

7 . The method of claim 6 , wherein the first trailer comprises a validity check for the first short packet container and the second short packet container.

8 . The method of claim 1 , wherein the short packet container further comprises:
a harmonic level number; and a packet payload length number.

9 . A switching structure comprising an electronic switch fabric, wherein the electronic switch fabric comprises:
a first plurality of rectangular orthogonal multiplexers, wherein the first plurality of rectangular orthogonal multiplexers is configured to receive a first plurality of container streams to produce a plurality of organized containers; a plurality of electronic switching cells electrically coupled to the first plurality of rectangular orthogonal multiplexers, wherein a switching cell of the plurality of switching cells is a time division multiplexing (TDM) switch, and wherein the plurality of electronic switching cells is configured to switch the plurality of organized containers to produce a plurality of switched containers; and a second plurality of rectangular orthogonal multiplexers electrically coupled to the plurality of electronic switching cells, wherein the second plurality of rectangular orthogonal multiplexers are configured to output a plurality of output containers.

10 . The switching structure of claim 9 , further comprising a photonic switch fabric, wherein the photonic switch fabric is configured to receive a second plurality of container streams from a packet splitter, and wherein the electronic switching fabric is configured to receive the first plurality of container streams from the packet splitter.

11 . The switching structure of claim 9 , wherein the plurality of electronic switching cells is a matrixed switch.

12 . The switching structure of claim 9 , wherein the plurality of electronic switching cells is a commutated switch.

13 . The switching structure of claim 9 , wherein the plurality of electronic switching cells is a matrixed commutating switch.

14 . The switching structure of claim 9 , wherein the switching cell comprises a data memory (DM) and a connection memory (CM) stack.

15 . The switching structure of claim 9 , wherein the switching cell is a double buffered TDM switch.

16 . A method comprising:
receiving a first address request for a first output port in a first timeslot on a first bus; receiving a second address request for the first output port in the first timeslot on the first bus; detecting a collision between the first address request and the second address request; writing the first address request to an electronic switching structure; and transmitting a negative acknowledgment message (NACK) corresponding to the second address request.

17 . The method of claim 16 , further comprising:
writing a third address request for the first output on a second bus to the electronic switching structure; detecting a collision between the third address and the first address; and selecting an output container corresponding to the third address.

18 . The method of claim 16 , wherein detecting the collision between the first address request and the second address request comprises:
selecting a first position in a memory for the first address request in accordance with the first timeslot and the first output; writing a first value in the first position in the memory; and selecting the first position in the memory for the second address request.

19 . The method of claim 18 , further comprising selecting a third position in the memory for the first address request in accordance with a second timeslot and the first output, wherein the second timeslot is directly after the first timeslot.

20 . The method of claim 16 , further comprising transmitting an acknowledgment frame (ACK) corresponding to the first address request.

21 . A method comprising:
receiving, from an electronic switch, a first container, wherein the first container comprises a first sequence number; extracting a first packet payload from the first container; determining a first packet in accordance with the first packet payload; receiving, from a photonic switch, a second container, wherein the second container comprises a second sequence number; extracting a second packet from the second container; and reconstructing a packet stream comprising the first packet and the second packet in accordance with the first sequence number and the second sequence number.

22 . The method of claim 21 , further comprising:
receiving, from the electronic switch, a third container; and extracting a second packet payload from the second container, wherein determining the first packet comprises forming the first packet in accordance with the first packet payload and the second packet payload.

23 . A method comprising:
comparing a length of a first packet to a threshold; determining that the first packet is a short packet when the length of the first packet is less than the threshold; determining that the first packet is a long packet when the length of the first packet is greater than or equal to the threshold; when the first packet is a long packet:
placing the packet in a long packet container, wherein the long packet container only contains one packet; and
transmitting the long packet container to a first synchronous framed switch; and
when the first packet is a short packet:
placing the packet in a short packet container, wherein the short packet container only contains one packet; and
transmitting the short packet container to a second synchronous

Assignees

• Huawei Tech Co Ltd

Inventors

• Graves Alan Frank

Classifications

• H04Q2011/0039

  Electrical control · CPC title

• H04Q2011/005

  Arbitration and scheduling · CPC title

• H04Q2011/0045

  Synchronisation · CPC title

• H04Q11/0005

  Switch and router aspects · CPC title

• H04Q11/0003 Primary

  Details · CPC title