Apparatus and method for measuring power supply noise

Patent metadata

Field	Value
Publication number	US-2016337048-A1
Application number	US-201514710466-A
Country	US
Kind code	A1
Filing date	May 12, 2015
Priority date	May 12, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

Described is an apparatus which comprises: a power delivery distribution network (PDN) to provide a power supply to at least one circuit; and an on-die synchronous power supply noise injector to inject noise to the power supply on the PDN. Described is another apparatus which comprises: a PDN to provide power supply to various circuits; an on-die power supply noise (PSN) sampler to sample the power supply with an injected noise, wherein the PSN sampler to sample the power supply with at least two different clock signals; and a phase noise accumulator to randomize the periods of the at least two different clock signals.

First claim

1 . An apparatus comprising:
a power delivery distribution network (PDN) to provide a power supply to at least one circuit; and an on-die synchronous power supply noise injector to inject noise to the power supply on the PDN; an on-die power supply noise (PSN) sampler to sample the power supply with an injected noise, wherein the PSN sampler is to sample the power supply with at least two different clock signals; and a phase noise accumulator to randomize periods of the at least two different clock signals, wherein the phase noise accumulator comprises a phase provider to provide phase signals and a phase selection multiplexer to receive the phase signals and to provide signals for generating the at least two different clock signals.

2 . (canceled)

3 . (canceled)

4 . The apparatus of claim 1 , wherein the phase selection multiplexer is
a glitch-free phase selection multiplexer.

5 . The apparatus of claim 4 , wherein the phase provider comprises a delay line with a plurality of delay elements to provide phase signals for the glitch-free phase selection multiplexer.

6 . The apparatus of claim 4 comprises a pseudorandom binary sequence (PRBS) generator coupled to the phase provider.

7 . The apparatus of claim 6 , wherein the PRBS generator is a phase noise source.

8 . The apparatus of claim 6 , wherein the PRBS generator is to generate signals for controlling the glitch-free phase selection multiplexer.

9 . The apparatus of claim 6 comprises at least two digital accumulators coupled to the PRBS generator, wherein the at least two digital accumulators are to generate two selection signals for controlling the glitch-free phase selection multiplexer.

10 . The apparatus of claim 1 , wherein the phase noise accumulator is to adjust a phase difference between the at least two different clock signals.

11 . The apparatus of claim 1 , wherein the on-die synchronous power supply noise injector is operable to inject a step noise to the power supply.

12 . The apparatus of claim 11 comprises logic which is operable to differentiate a response of the step noise to generate an impulse response.

13 . The apparatus of claim 12 comprises logic which is operable to perform discrete Fourier transform of the impulse response to generate an impedance profile of the PDN.

14 . An apparatus comprising:
a power delivery distribution network (PDN) to provide a power supply to at least one circuit; an on-die power supply noise (PSN) sampler to sample the power supply with an injected noise, wherein the PSN sampler is to sample the power supply with at least two different clock signals; and a phase noise accumulator to randomize the periods of the at least two different clock signals, wherein the phase noise accumulator comprises a phase provider to provide phase signals and a phase selection multiplexer to receive the phase signals and to provide signals for generating the at least two different clock signals.

15 . The apparatus of claim 14 comprises an on-die synchronous power supply noise injector to inject noise to the power supply on the PDN.

16 . The apparatus of claim 15 , wherein the on-die synchronous power supply noise injector is operable to inject a step noise to the power supply.

17 . The apparatus of claim 16 comprises:
logic which is operable to differentiate a response of the step noise to generate an impulse response; and
logic which is operable to perform discrete Fourier transform of the impulse response to generate an impedance profile of the PDN.

18 . A system comprising:
a memory; a processor coupled to the memory, the processor comprising:
a power delivery distribution network (PDN) to provide a power supply to at least one circuit; and
an on-die synchronous power supply noise injector to inject noise to the power supply on the PDN;
an on-die power supply noise (PSN) sampler to sample the power supply with an injected noise, wherein the PSN sampler is to sample the power supply with at least two different clock signals; and
a phase noise accumulator to randomize periods of the at least two different clock signals, wherein the phase noise accumulator comprises a phase provider to provide phase signals and a phase selection multiplexer to receive the phase signals and to provide signals for generating the at least two different clock signals; and
a wireless interface for allowing the processor to communicate with another device.

19 . (canceled)

20 . (canceled)

Assignees

• Intel Corp

Inventors

• Hsueh Tzu-Chien
• O'Mahony Frank

Classifications

• H04B15/005 Primary

  Reducing noise, e.g. humm, from the supply · CPC title

• H04B17/104

  of other parameters, e.g. DC offset, delay or propagation times · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• H04B17/345 Primary

  Interference values ({signal-to-interference ratio [SIR] or carrier-to-interference ratio [CIR]} H04B17/336) · CPC title

• G01R31/31709

  Jitter measurements; Jitter generators (measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901) · CPC title