Glitch-free digitally controlled oscillator code update

Patent metadata

Field	Value
Publication number	US-2016336943-A1
Application number	US-201514713174-A
Country	US
Kind code	A1
Filing date	May 15, 2015
Priority date	May 15, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

A glitch-free digitally controlled oscillator (DCO) code update may be achieved by synchronizing the transfer of the DCO code update to a logic state transition of a pulse in the DCO clock output signal such that the code update may be achieved while the DCO delay chain remains in the same logic state. A state machine may provide the DCO code update and a pulsed update signal to a timing circuit. The DCO code update may be aligned with a pulse in the pulsed update signal. The timing circuit may generate a DCO code update enabled signal upon alignment of the pulse in the pulsed update signal with a state transition of a pulse in the pulsed DCO clock output. The DCO code update enabled signal may be aligned with a state transition in the pulsed DCO clock output to permit a glitch-free DCO code update.

First claim

1 . A system for synchronizing digitally controlled oscillator (DCO) code updates, the system comprising:
at least one storage device to receive a DCO code update, the at least one storage device communicably coupled to a DCO; and at least one timing circuit communicably coupled to the at least one storage device and to the DCO, the at least one timing circuit to:
align a logic state transition in a pulse in a pulsed clock output provided by the DCO with a logic state transition of a pulse in a pulsed update signal received with the DCO code update; and
cause a transfer of the DCO code update from the at least one storage device to the DCO responsive to an alignment of the logic state transition in the pulse of the pulsed DCO clock output with the logic state transition of the pulse in the pulsed update signal.

2 . The system of claim 1 , further comprising:
a state machine to provide the pulsed update signal and the DCO code update; wherein the DCO code update is aligned with the logic state transition of the pulse in the update signal.

3 . The system of claim 2 wherein the at least one timing circuit generates a DCO update enabled signal that includes at least one pulse, the at least one pulse of the DCO update enabled signal aligned with one of: a leading edge of the pulse in the pulsed DCO clock output signal or a trailing edge of the pulse in the pulsed DCO clock output signal.

4 . The system of claim 3 wherein the at least one timing circuit comprises a plurality of cascaded flip-flops.

5 . The system of claim 4 wherein the at least one timing circuit comprises a first pair of flip-flops to align the logic state transition in the pulse in the pulsed DCO clock output with the logic state transition of the pulse in the update signal received with the DCO code update.

6 . The system of claim 5 wherein the timing circuit comprises a second pair of D flip-flops to generate the DCO update enabled signal.

7 . The system of claim 1 wherein the pulse width of the at least one pulse included in the pulsed update signal is at least equal to a period of the pulsed DCO clock output signal.

8 . A method for updating a digitally controlled oscillator (DCO), the method comprising:
generating, by a state machine, a pulsed update signal; aligning, by the state machine, a DCO code update with a logic state transition of a pulse in the pulsed update signal; storing the DCO code update in a memory communicably coupled to the state machine; synchronizing, by a timing circuit, a logic state transition of a pulsed DCO clock output signal with the logic state transition of the pulse in the pulsed update signal; and transferring the DCO code update from the memory to the DCO responsive to the synchronization of the logic state transition of a pulse in the pulsed DCO clock output signal with the logic state transition of the pulse in the pulsed update signal.

9 . The method of claim 8 wherein transferring the DCO code update from the memory to the DCO responsive to the synchronization of the logic state transition of a pulse in the pulsed DCO clock output signal with the logic state transition of the pulse in the pulsed update signal comprises:
generating, by the timing circuit, a DCO update enabled signal responsive to the synchronization of the logic state transition of the pulse in the pulsed DCO clock output signal with the logic state transition of the pulse in the pulsed update signal; and
transmitting the DCO update enabled signal to the memory.

10 . The method of claim 9 wherein synchronizing a logic state transition of a pulse in the pulsed DCO clock output signal with the logic state transition of the pulse in the pulsed update signal comprises:
synchronizing the logic state transition of the pulse in the pulsed DCO clock output signal with the logic state transition of the pulse in the pulsed update signal by a timing circuit that includes a plurality of serially cascaded flip-flops.

11 . The method of claim 10 wherein synchronizing the logic state transition of the pulse in the DCO clock output signal with the logic state transition of the pulse in the pulsed update signal comprises:
synchronizing the logic state transition of the pulse in the DCO clock output signal with the logic state transition of the pulse in the pulsed update signal by a timing circuit that includes a first pair of serially cascaded D flip-flops.

12 . The method of claim 11 wherein generating, by the timing circuit, a DCO update enabled signal comprises:
generating the DCO update enabled signal by a timing circuit that includes a second pair of serially cascaded D flip-flops, the second pair of serially cascaded D flip-flops coupled in series with the first pair of serially cascaded D flip-flops.

13 . The method of claim 9 wherein generating a DCO update enabled signal responsive to the synchronization of the logic state transition of a pulse in the pulsed DCO clock output signal with the logic state transition of the pulse in the pulsed update signal comprises:
generating, by the timing circuit, a DCO update enabled signal that includes at least one pulse having a width at least equal to the defined period of the pulse in the pulsed DCO clock output signal.

14 . The method of claim 13 wherein generating, by the timing circuit, a DCO update enabled signal that includes a pulse having a width at least equal to the defined period of the pulse in the pulsed DCO clock output signal comprises:
aligning, by the timing circuit, the at least one pulse in the DCO update enabled signal with one of: a leading edge of a pulse in the pulsed DCO clock output signal or a trailing edge of a pulse in the pulsed DCO clock output signal.

15 . A non-transitory machine-readable medium comprising machine readable instructions that when executed:
cause a state machine communicably coupled to a digitally controlled oscillator (DCO) to generate a pulsed update signal; cause the state machine to align a DCO code update with a logic state transition of a pulse in the pulsed update signal; cause the state machine to store the DCO code update in a memory communicably coupled to the state machine; cause the state machine to transfer the DCO code update from the memory to the DCO responsive to the synchronization of the logic state transition of a pulse in the pulsed DCO clock output signal with the logic state transition of the pulse in the pulsed update signal.

16 . The non-transitory machine readable medium of claim 15 wherein the machine readable instructions that cause the state machine to transfer the DCO code update from the memory to the DCO responsive to the synchronization of the logic state transition of a pulse in the pulsed DCO clock output signal with the logic state transition of the pulse in the pulsed update signal further:
cause the state machine to transfer the DCO code update from the memory to the DCO responsive to the receipt of a DCO update enabled signal generated by a timing circuit responsive to the synchronization of the logic state transition of a pulse in the pulsed DCO clock output signal with the logic state transition of the pulse in the pulsed update signal.

17 . The non-transitory machine readable medium of claim 16 wherein the machine readable instructions that cause the state machine to transfer the DCO code update from the memory to the DCO responsive to the receipt of a DCO update enabled signal generated by a timing circuit responsive to the synchronization of the logic state transition of a pulse in the pulsed DCO clock output signal with the logi

Assignees

• Intel Corp

Inventors

• Wei Fangxing
• Allen Michael J
• Shah Setul M

Classifications

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/095

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/0991 Primary

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title