Phase correction in a doherty power amplifier

Patent metadata

Field	Value
Publication number	US-2016336903-A1
Application number	US-201514714036-A
Country	US
Kind code	A1
Filing date	May 15, 2015
Priority date	May 15, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

In various embodiments, a semiconductor package includes a carrier amplifier connected to a first output of a power divider, and a first output matching network connected to the carrier amplifier and an output combining node. The first output matching network exhibits a phase delay during operation of the carrier amplifier. The semiconductor package includes a phase advance network connected to the first output matching network. The phase advance network is configured to offset at least a portion of the phase delay of the first output matching network. The semiconductor package includes a peaking amplifier connected to a second output of the power divider and the output combining node, and a second output matching network connected to the peaking amplifier.

First claim

1 . A device, comprising:
a Doherty amplifier having a carrier path and a peaking path, the carrier path including:
a carrier amplifier configured to amplify a signal received from an input to the Doherty amplifier,
an output matching network connected directly to an output of the carrier amplifier, the output matching network exhibiting a phase delay during operation of the Doherty amplifier, and
a phase advance network connected directly to an output of the output matching network and a combining node of the Doherty amplifier, the phase advance network being configured to offset at least a portion of the phase delay of the output matching network, wherein a phase length of the carrier path from the carrier amplifier to a combining node of the Doherty amplifier is approximately λ/4, where λ is a wavelength of an operating frequency of the Doherty amplifier.

2 . The device of claim 1 , wherein the phase advance network includes a high-pass filter.

3 . The device of claim 2 , wherein the high-pass filter is configured as a shunt-inductive network.

4 . The device of claim 2 , wherein a cutoff frequency of the high-pass filter is less than an operating frequency of the Doherty amplifier.

5 . The device of claim 1 , wherein the Doherty amplifier is configured as an inverted Doherty amplifier.

6 . The device of claim 1 , wherein the carrier amplifier and the phase advance network are in the same package.

7 . (canceled)

8 . A semiconductor package, comprising:
a carrier amplifier connected to a first output of a power divider; a first output matching network connected to the carrier amplifier and an output combining node, the first output matching network exhibiting a phase delay during operation of the carrier amplifier; a phase advance network connected to an output of the first output matching network, the phase advance network being configured to offset at least a portion of the phase delay of the first output matching network; a peaking amplifier connected to a second output of the power divider and the output combining node; and a second output matching network connected to the peaking amplifier.

9 . The semiconductor package of claim 8 , wherein the phase advance network includes a high-pass filter.

10 . The semiconductor package of claim 9 , wherein the high-pass filter is configured as a shunt-inductive network.

11 . The semiconductor package of claim 9 , wherein a cutoff frequency of the high-pass filter is less than an operating frequency of the carrier amplifier.

12 . The semiconductor package of claim 8 , where a phase length from the carrier amplifier to the output combining node is approximately λ/4, where λ is a wavelength of an operating frequency of the carrier amplifier.

13 . The semiconductor package of claim 8 , wherein the carrier amplifier and the peaking amplifier are in an inverted Doherty amplifier configuration.

14 . A device, comprising:
a first amplifier path connected to a first output of a power divider, the first amplifier path including a first amplifier; a phase advance network coupled to the first amplifier path between the first amplifier and an output combining node connected to the first amplifier path, the phase advance network being configured to offset at least a portion of a phase delay of a component connected to the first amplifier path; and a second amplifier path connected to a second output of the power divider and the output combining node.

15 . The device of claim 14 , wherein the phase advance network includes a high-pass filter.

16 . The device of claim 15 , wherein the high-pass filter is configured as a shunt-inductive network.

17 . The device of claim 15 , wherein a cutoff frequency of the high-pass filter is less than an operating frequency of an amplifier connected to the first amplifier path.

18 . (canceled)

19 . The device of claim 14 , wherein where a phase length from an amplifier of the first amplifier path to the output combining node is approximately λ/4, where λ is a wavelength of an operating frequency of the amplifier.

20 . The device of claim 14 , wherein the first amplifier path and the second amplifier path are in an inverted Doherty amplifier configuration.

Assignees

• Ahmed Maruf
• Staudinger Joseph
• Freescale Semiconductor Inc

Inventors

• Ahmed Maruf
• Staudinger Joseph

Classifications

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F3/195

  in integrated circuits · CPC title

• H03F3/19

  with semiconductor devices only · CPC title

• H03F1/565

  using inductive elements · CPC title

• H03F2200/391

  the output circuit of an amplifying stage comprising an LC-network · CPC title