Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016336457-A1
Application number	US-201615221656-A
Country	US
Kind code	A1
Filing date	Jul 28, 2016
Priority date	Jul 12, 2013
Publication date	Nov 17, 2016
Grant date	—

Abstract

To give favorable electrical characteristics to a semiconductor device. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a pair of electrodes over the semiconductor layer and each electrically connected to the semiconductor layer, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The insulating layer includes an island-shaped projecting portion. A top surface of the projecting portion of the insulating layer is in contact with a bottom surface of the semiconductor layer, and is positioned on an inner side of the semiconductor layer when seen from above. The pair of electrodes covers part of a top surface and part of side surfaces of the semiconductor layer. Furthermore, the gate electrode and the gate insulating layer cover side surfaces of the projecting portion of the insulating layer.

First claim

What is claimed is:

1 . A semiconductor device comprising:
an insulating layer; a metal oxide layer over the insulating layer; a first electrode and a second electrode over and electrically connected to the metal oxide layer; a gate electrode over the metal oxide layer; and a gate insulating layer between the metal oxide layer and the gate electrode, wherein the insulating layer includes a projecting portion, wherein a top surface of the projecting portion is positioned inside an outline of the metal oxide layer when seen in a plan view, wherein the first electrode and the second electrode cover first parts of a top surface and first parts of side surfaces of the metal oxide layer, and wherein the gate electrode and the gate insulating layer cover a second part of the top surface and second parts of the side surfaces of the metal oxide layer and first side surfaces of the projecting portion of the insulating layer.

2 . The semiconductor device according to claim 1 ,
wherein the metal oxide layer comprises an oxide semiconductor.

3 . The semiconductor device according to claim 1 ,
wherein the metal oxide layer comprises indium, gallium, and zinc.

4 . The semiconductor device according to claim 1 ,
wherein a bottom surface of the gate electrode is positioned below the top surface of the projecting portion.

5 . The semiconductor device according to claim 1 ,
wherein the first electrode and the second electrode cover second side surfaces of the projecting portion.

6 . The semiconductor device according to claim 1 ,
wherein the gate insulating layer covers part of a surface of the metal oxide layer in a downward direction.

7 . The semiconductor device according to claim 1 , further comprising:
a bottom oxide layer between the metal oxide layer and the insulating layer, wherein the bottom oxide layer has a shape that is substantially aligned with a shape of the metal oxide layer when seen in the plan view.

8 . The semiconductor device according to claim 1 , further comprising:
a top oxide layer between the metal oxide layer and the gate insulating layer, wherein the top oxide layer has a shape that is substantially aligned with a shape of the metal oxide layer when seen in the plan view.

9 . The semiconductor device according to claim 1 , further comprising:
a top oxide layer between the metal oxide layer and the gate insulating layer, wherein the top oxide layer has a shape that is substantially aligned with a shape of the gate electrode when seen in the plan view.

10 . The semiconductor device according to claim 1 ,
wherein the gate electrode overlaps with the first electrode and with the second electrode.

11 . An electronic device comprising the semiconductor device according to claim 1 .

12 . A semiconductor device comprising:
an insulating layer; a metal oxide layer over the insulating layer; a first electrode and a second electrode over and electrically connected to the metal oxide layer; a gate electrode over the metal oxide layer; a gate insulating layer between the metal oxide layer and the gate electrode; a bottom oxide layer between the insulating layer and the metal oxide layer; and a top oxide layer between the metal oxide layer and the gate insulating layer, wherein the insulating layer includes a projecting portion, wherein a top surface of the projecting portion is positioned inside an outline of the metal oxide layer when seen in a plan view, wherein the first electrode and the second electrode cover first parts of a top surface of the top oxide layer and first parts of side surfaces of the metal oxide layer, wherein the gate electrode and the gate insulating layer cover a second part of the top surface and second parts of the side surfaces of the metal oxide layer and first side surfaces of the projecting portion of the insulating layer, and wherein the bottom oxide layer and the top oxide layer have a shape that is substantially aligned with a shape of the metal oxide layer when seen in the plan view.

13 . The semiconductor device according to claim 12 ,
wherein the first electrode and the second electrode are between the gate insulating layer and the top oxide layer.

14 . The semiconductor device according to claim 12 ,
wherein the gate insulating layer covers part of a surface of the bottom oxide layer in a downward direction.

15 . The semiconductor device according to claim 12 ,
wherein the first electrode and the second electrode cover second side surfaces of the projecting portion.

16 . The semiconductor device according to claim 12 ,
wherein the bottom oxide layer and the top oxide layer each contain one or more of metal elements contained in the metal oxide layer.

17 . The semiconductor device according to claim 12 ,
wherein the bottom oxide layer, the metal oxide layer, and the top oxide layer each comprises indium, gallium, and zinc.

18 . The semiconductor device according to claim 12 ,
wherein a bottom surface of the gate electrode is positioned below the top surface of the projecting portion.

19 . An electronic device comprising the semiconductor device according to claim 12 .

20 . A semiconductor device comprising:
an insulating layer; a metal oxide layer over the insulating layer; a first electrode and a second electrode over and electrically connected to the metal oxide layer; a gate electrode over the metal oxide layer; a gate insulating layer between the metal oxide layer and the gate electrode; a bottom oxide layer between the insulating layer and the metal oxide layer; and a top oxide layer between the metal oxide layer and the gate insulating layer, wherein the insulating layer includes a projecting portion, wherein a top surface of the projecting portion is positioned inside an outline of the metal oxide layer when seen in a plan view, wherein the first electrode and the second electrode cover first parts of a top surface and first parts of side surfaces of the metal oxide layer, wherein the gate electrode and the gate insulating layer cover a second part of the top surface and second parts of the side surfaces of the metal oxide layer and first side surfaces of the projecting portion of the insulating layer, wherein the bottom oxide layer has a shape that is substantially aligned with a shape of the metal oxide layer when seen in the plan view, and wherein the top oxide layer has a shape that is substantially aligned with a shape of the gate electrode when seen in the plan view.

21 . The semiconductor device according to claim 20 ,
wherein the first electrode and the second electrode are between the metal oxide layer and the top oxide layer.

22 . The semiconductor device according to claim 20 ,
wherein the top oxide layer covers part of a surface of the bottom oxide layer in a downward direction and the first side surfaces of the projecting portion.

23 . The semiconductor device according to claim 20 ,
wherein a bottom surface of the gate electrode is positioned below the top surface of the projecting portion.

24 . The semiconductor device according to claim 20 ,
wherein the bottom oxide layer and the top oxide layer each contain one or more of metal elements contained in the metal oxide layer.

25 . The semiconductor device according to claim 20 ,
wherein the bottom oxide layer, the metal oxide layer, and the top oxide layer ea

Assignees

• Semiconductor Energy Lab

Inventors

• Sasagawa Shinya
• Kurata Motomu

Classifications

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D62/402

  Amorphous materials · CPC title