Short circuit reduction in a ferroelectric memory cell comprising a stack of layers arranged on a flexible substrate

Patent metadata

Field	Value
Publication number	US-2016336334-A1
Application number	US-201615222092-A
Country	US
Kind code	A1
Filing date	Jul 28, 2016
Priority date	Jun 27, 2011
Publication date	Nov 17, 2016
Grant date	—

Abstract

A ferroelectric memory cell ( 1 ) and a memory device ( 100 ) comprising one or more such cells ( 1 ). The ferroelectric memory cell comprises a stack ( 4 ) of layers arranged on a flexible substrate ( 3 ). Said stack comprises an electrically active part ( 4 a ) and a protective layer ( 11 ) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer ( 5 ) and a top electrode layer ( 9 ) and at least one ferroelectric memory material layer ( 7 ) between said electrodes. The stack further comprises a buffer layer ( 13 ) arranged between the top electrode layer ( 9 ) and the protective layer ( 11 ). The buffer layer ( 13 ) is adapted for at least partially absorbing a lateral dimensional change (ΔL) occurring in the protective layer ( 11 ) and thus preventing said dimensional change (ΔL) from being transferred to the electrically active part ( 4 a ), thereby reducing the risk of short circuit to occur between the electrodes.

First claim

1 - 21 . (canceled)

22 . A method of using a material with a glass transition temperature that is lower than 30 degrees C. for forming a buffer layer for reduction of short circuits in a ferroelectric memory cell, the method comprising:
arranging a buffer layer between a top electrode layer and a protective layer in the ferroelectric memory cell; and arranging a stack of layers on a flexible substrate, wherein said stack comprises an electrically active part and a protective hard layer for protecting the electrically active part against scratches and abrasion, wherein said electrically active part comprises a bottom electrode layer and a top electrode layer and at least one ferroelectric memory material layer between said electrodes.

23 . A method for producing a ferroelectric memory cell comprising a stack of layers arranged on a flexible substrate, said method comprising:
providing said substrate and arranged thereon an electrically active part of said stack, the electrically active part comprising a bottom electrode layer and a top electrode layer separated by at least one ferroelectric memory material layer; providing a protective layer for protecting the electrically active part against scratches and abrasion; and wherein the method further comprises one or both of the following steps: providing a buffer layer on top of said electrically active part of said stack before providing the protective layer, the buffer layer being adapted for at least partially absorbing a lateral dimensional change occurring in the protective layer and thus preventing said dimensional change from being transferred to the electrically active part by being of a coherent material and having such layer thickness that a lateral dimensional deformation in a top portion of the buffer layer facing the protective layer results in substantially less lateral dimensional deformation in a bottom portion facing the electrically active part, when said lateral dimensional deformation in the upper part is caused by the lateral dimensional change of the protective layer, the difference in lateral deformation between the top and bottom portions corresponding to absorbed lateral dimensional change; and electrically operating the electrically active part before providing the protective layer.

24 . The method as claimed in claim 23 , wherein providing the protective layer involves depositing a layer in a fluid form and subsequently hardening the deposited layer, such as by curing.

25 . The method as claimed in claim 23 , further comprising providing the electrically active part and/or the buffer layer by printing.

26 - 27 . (canceled)

28 . A method for producing a ferroelectric memory cell comprising a stack of layers arranged on a flexible substrate, said method comprising:
providing said substrate and arranged thereon an electrically active part of said stack, the electrically active part comprising a bottom electrode layer and a top electrode layer separated by at least one ferroelectric memory material layer, wherein the top electrode layer has a top surface facing the protective layer; providing a protective layer for protecting the electrically active part against scratches and abrasion; and providing a buffer layer on top of said electrically active part of said stack before providing the protective layer, the buffer layer being adapted for at least partially absorbing a lateral dimensional change occurring in the protective layer and thus preventing said dimensional change from being transferred to the electrically active part, wherein the buffer layer is formed of a non-coherent material confined between the protective layer and the top electrode layer, wherein the non-coherent material is a gas, the buffer layer preferably corresponding to a gas filled gap, such as a gap filled with carbon dioxide or an air-gap, and wherein the buffer layer extends along the entire top surface of the top electrode layer.

Assignees

• Thin Film Electronics Asa

Inventors

• Karlsson Christer
• Hagel Olle Jonny
• Nilsson Jakob
• Bröms Per

Classifications

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• G11C11/22

  using ferroelectric elements · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11B9/02 Primary

  using ferroelectric record carriers; Record carriers therefor · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title