Semiconductor device including an electrode lower layer and an electrode upper layer and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2016336333-A1
Application number	US-201615221756-A
Country	US
Kind code	A1
Filing date	Jul 28, 2016
Priority date	Sep 26, 2008
Publication date	Nov 17, 2016
Grant date	—

Abstract

A semiconductor device includes a lower electrode, a ferroelectric film on the lower electrode, an upper electrode on the ferroelectric film, and a first insulating film covering a surface and a side of the upper electrode, a side of the ferroelectric film, and a side of the lower electrode. The first insulating film includes a first opening that exposes a portion of the surface of the upper electrode. A second insulating film covers the first insulating film and includes a second opening that exposes the portion of the surface of the upper electrode through a second opening. A barrier metal is formed in the first opening and the second opening, and is connected to the upper electrode. A connection region in which a material of the barrier metal interacts with a material of the upper electrode extends below an upper-most surface of the upper electrode.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
(a) a lower electrode; (b) a ferroelectric film formed on the lower electrode; (c) an upper electrode formed on the ferroelectric film; (d) a first insulating film covering a surface and a side of the upper electrode, a side of the ferroelectric film, and a side of the lower electrode, and exposing a portion of the surface of the upper electrode through a first opening; (e) a second insulating film covering the first insulating film and exposing the portion of the surface of the upper electrode through a second opening which is connected to the first opening; (f) a barrier metal formed in the first opening and the second opening, and connected to the upper electrode; (g) a conductive portion formed on the barrier metal; (h) wherein the surface of the upper electrode has a recess, and (i) the barrier metal is formed from a wall of the second opening to a surface of the recess.

2 . The semiconductor device of claim 1 , wherein the conductive portion is embedded in the first opening and the second opening.

3 . The semiconductor device of claim 1 , wherein the deepest portion of the conductive portion is arranged on an intermediate portion in the depth direction of the first opening.

4 . The semiconductor device of claim 1 , wherein the conductive portion is made of tungsten.

5 . The semiconductor device of claim 1 , wherein
the upper electrode includes an electrode lower layer having an irregular upper surface and an electrode upper layer stacked on the electrode lower layer, and the electrode upper layer has a smooth upper surface relative to and independent of the irregular upper surface of the electrode lower layer.

6 . The semiconductor device of claim 5 , wherein
the ferroelectric film has an irregular upper surface, and the electrode upper layer has a smooth upper surface relative to and independent of the irregular upper surface of the ferroelectric film.

7 . The semiconductor device of claim 5 , wherein the electrode lower layer is comprised of an IrO 2 film, an Ir film or an IrTa alloy film.

8 . The semiconductor device of claim 5 , wherein the electrode upper layer is comprised of a material containing Ti.

9 . The semiconductor device of claim 5 , wherein the upper surface of the electrode upper layer is formed with a planarizing process.

10 . The semiconductor device of claim 1 , wherein the first insulating film is a conformal layer.

11 . A semiconductor device, comprising:
(a) a lower electrode; (b) a ferroelectric film formed on the lower electrode; (c) an upper electrode formed on the ferroelectric film; (d) a first insulating film covering a surface and a side of the upper electrode, a side of the ferroelectric film, and a side of the lower electrode, and exposing a portion of the surface of the upper electrode through a first opening; (e) a second insulating film covering the first insulating film and exposing the portion of the surface of the upper electrode through a second opening which is connected to the first opening; (f) a barrier metal formed in the first opening and the second opening, and connected to the upper electrode; (g) a conductive portion formed on the barrier metal; (h) wherein the upper electrode includes a first portion and a second portion, the first portion is reacted with the barrier metal so that the first portion interdigitates with the second portion of the upper electrode, the second portion being unreacted with the barrier metal.

12 . The semiconductor device of claim 11 , wherein the conductive portion is embedded in the first opening and the second opening.

13 . The semiconductor device of claim 11 , wherein the deepest portion of the conductive portion is located in the first opening, above an upper-most surface of the upper electrode.

14 . The semiconductor device of claim 11 , wherein the conductive portion is made of tungsten.

15 . The semiconductor device of claim 11 , wherein
the upper electrode includes an electrode lower layer having an irregular upper surface and an electrode upper layer stacked on the electrode lower layer, and the electrode upper layer has a smooth upper surface relative to and independent of the irregular upper surface of the electrode lower layer.

16 . The semiconductor device of claim 15 , wherein
the ferroelectric film has an irregular upper surface, and the electrode upper layer has a smooth upper surface relative to and independent of the irregular upper surface of the ferroelectric film.

17 . The semiconductor device of claim 15 , wherein the electrode lower layer is comprised of an IrO 2 film, an Ir film or an IrTa alloy film.

18 . The semiconductor device of claim 15 , wherein the electrode upper layer is comprised of a material containing Ti.

19 . The semiconductor device of claim 15 , wherein the upper surface of the electrode upper layer is formed with a planarizing process.

20 . A semiconductor device, comprising:
a lower electrode; a ferroelectric film formed on the lower electrode; an upper electrode formed on the ferroelectric film; a first insulating film covering an upper surface of the upper electrode, a side of the ferroelectric film, and a side of the lower electrode, and exposing a portion of the surface of the upper electrode through a first opening; a second insulating film covering the first insulating film and exposing the portion of the surface of the upper electrode through a second opening in the second insulating film; a barrier metal lining walls of the first opening and the second opening, and covering the portion of the surface of the upper electrode exposed by the first opening in the first insulating film and the second opening in the second insulating film, such that a connection region in which a material of the barrier metal interacts with a material of the upper electrode extends beneath an upper-most surface of the upper electrode.

Assignees

• Rohm Co Ltd

Inventors

• Nakao Yuichi

Classifications

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/694

  comprising noble metals or noble metal oxides · CPC title

• H10D1/692

  Electrodes · CPC title

• H10D1/688

  comprising barrier layers to prevent diffusion of hydrogen or oxygen · CPC title

• H10D1/682 Primary

  having dielectrics comprising perovskite structures · CPC title