Semiconductor package and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2016336303-A1
Application number	US-201615063433-A
Country	US
Kind code	A1
Filing date	Mar 7, 2016
Priority date	May 14, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

A semiconductor package includes a semiconductor die having an active surface and a bottom surface opposite to the active surface; a plurality of bond pads distributed on the active surface of the semiconductor die; an encapsulant covering the active surface of the semiconductor die, wherein the encapsulant comprises a bottom surface that is flush with the bottom surface of the semiconductor; and a plurality of printed interconnect features embedded in the encapsulant for electrically connecting the plurality of bond pads. Each of the printed interconnect features comprises a conductive wire and a conductive pad being integral with the conductive wire.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a first semiconductor die having an active surface and a bottom surface opposite to the active surface; a plurality of input/output (I/O) pads distributed on the active surface of the first semiconductor die; an encapsulant covering the active surface of the first semiconductor die, wherein the encapsulant comprises a bottom surface that is flush with the bottom surface of the semiconductor; and a plurality of printed interconnect features embedded in the encapsulant for electrically connecting the plurality of I/O pads, wherein each of the printed interconnect features comprises a conductive wire and a conductive pad being integral with the conductive wire.

2 . The semiconductor package according to claim 1 , wherein the conductive pad is disposed around the first semiconductor die on the bottom surface of the encapsulant, and wherein the conductive pad has an exposed bottom surface that is flush with the bottom surface of the encapsulant.

3 . The semiconductor package according to claim 1 , wherein the conductive wire and the conductive pad are integrally formed by using a three-dimensional (3D) printer.

4 . The semiconductor package according to claim 1 , wherein the printed interconnect features comprise silver, gold, copper, carbon nanotube, graphine, or nano metal particles.

5 . The semiconductor package according to claim 1 , wherein the encapsulant comprises an epoxy, a resin, or a moldable polymer.

6 . The semiconductor package according to claim 1 , wherein the bottom surface of the first semiconductor die is not covered by the encapsulant.

7 . The semiconductor package according to claim 1 , wherein the conductive wire comprises a widened portion disposed adjacent to a top surface of the encapsulant.

8 . The semiconductor package according to claim 7 , wherein the widened portion comprises a pad.

9 . The semiconductor package according to claim 8 , wherein an opening is formed in the top surface of the encapsulant to expose the pad.

10 . The semiconductor package according to claim 9 , wherein a conductive element is disposed in the opening and on the pad.

11 . The semiconductor package according to claim 10 , wherein a die package is mounted on the top surface of the encapsulant and is electrically connected to the conductive element.

12 . The semiconductor package according to claim 1 further comprising a passive device embedded in the encapsulant and electrically connected to the printed interconnect features.

13 . The semiconductor package according to claim 1 further comprising a second semiconductor die adhesively secured to the top surface of the first semiconductor die.

14 . The semiconductor package according to claim 13 , wherein the second semiconductor die partially overlaps with the first semiconductor die when viewed from above.

15 . A semiconductor package, comprising:
a semiconductor die having an active surface and a bottom surface opposite to the active surface; a plurality of input/output (I/O) pads distributed on the active surface of the first semiconductor die; an encapsulant covering the active surface of the semiconductor die, wherein the encapsulant comprises a bottom surface that is flush with the bottom surface of the semiconductor; and a plurality of printed conductive wires embedded in the encapsulant for electrically connecting the plurality of I/O pads, wherein each of the printed conductive wires comprises a portion bent at right angles.

16 . The semiconductor package according to claim 1 further comprising conductive pads disposed around the semiconductor die on the bottom surface of the encapsulant, and wherein each of the conductive pads has an exposed bottom surface that is flush with the bottom surface of the encapsulant.

17 . A method for fabricating a semiconductor package, comprising:
providing a carrier; arranging semiconductor dice on the carrier, wherein each of the semiconductor dice has a top surface or active surface and a bottom surface that is opposite to the active surface, and wherein a plurality of input/output (I/O) pads are distributed on the active surface; printing interconnect features comprising conductive pads and conductive wires on the carrier and on the top surfaces of the semiconductor dice; encapsulating the top surface of the carrier, the top surfaces of the semiconductor dice, the conductive wires, and the conductive pads with an encapsulant; and removing the carrier.

18 . The method for fabricating a semiconductor package according to claim 17 , wherein the carrier comprises glass, silicon, or metal.

19 . The method for fabricating a semiconductor package according to claim 17 , wherein the conductive wires are integrally formed with the conductive pads.

20 . The method for fabricating a semiconductor package according to claim 17 , wherein the interconnect features are composed of silver, gold, copper, carbon nanotube, graphine, or nano metal particles.

21 . The method for fabricating a semiconductor package according to claim 17 , wherein the conductive wires and the conductive pads are formed by using a 3D printer or a wire bonding tool having 3D printing function.

22 . The method for fabricating a semiconductor package according to claim 17 , wherein after the formation of the connecting elements, a dicing process is performed to singulate individual semiconductor packages from one another.

23 . A method for fabricating a semiconductor package, comprising:
providing a carrier; arranging a semiconductor die on the carrier; printing temporary interconnect features on the carrier and on the top surfaces of the semiconductor die; encapsulating the top surface of the carrier, the top surfaces of the semiconductor die, the temporary interconnect features with an encapsulant; removing the carrier; removing the temporary interconnect features thereby forming cavity in the encapsulant; and filling the cavity with conductive material to form interconnect features.

24 . The method for fabricating a semiconductor package according to claim 23 , wherein the interconnect features conductive pads and conductive wires, and wherein the conductive wires are integrally formed with the conductive pads.

25 . The method for fabricating a semiconductor package according to claim 23 , wherein the temporary interconnect features are composed of a non-conductive material or an ashable material.

26 . The method for fabricating a semiconductor package according to claim 23 , wherein the the interconnect features are composed of silver, gold, copper, carbon nanotube, graphine, nano metal particles, or solder.

Assignees

• Mediatek Inc

Inventors

• Tsai Shiann-Tsong

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/752

  between stacked chips · CPC title