Surface-Mountable Multi-Chip Component

Patent metadata

Field	Value
Publication number	US-2016336301-A1
Application number	US-201515111775-A
Country	US
Kind code	A1
Filing date	Jan 30, 2015
Priority date	Jan 31, 2014
Publication date	Nov 17, 2016
Grant date	—

Abstract

A surface-mountable multi-chip component includes a carrier having a first connection element, a second connection element and third connection element that are electrically insulated from one another. A first semiconductor chip is arranged on the first connection element and electrically connected to the first and second connection elements. The first connection element forms a first electrode and the second connection element forms a second electrode for the first semiconductor chip. A second semiconductor chip is arranged on the second connection element and electrically connected to the second and third connection elements. The third connection element forms a first electrode and the second connection element forms a second electrode for the second semiconductor chip. The second connection element forms a common cathode or anode for the first and second semiconductor chips during operation.

First claim

1 - 16 . (canceled)

17 . A surface-mountable multi-chip component comprising:
a carrier having a first connection element, a second connection element and third connection element that are electrically insulated from one another; a first semiconductor chip arranged on the first connection element and electrically connected to the first and second connection elements, wherein the first connection element forms a first electrode and the second connection element forms a second electrode for the first semiconductor chip; and a second semiconductor chip arranged on the second connection element and electrically connected to the second and third connection elements, wherein the third connection element forms a first electrode and the second connection element forms a second electrode for the second semiconductor chip, and wherein the second connection element forms a common cathode or anode for the first and second semiconductor chips during operation.

18 . The surface-mountable multi-chip component according to claim 17 , wherein
the first connection element has a first partial region; the second connection element has a first partial region, a second partial region and a central region, via which the first partial region of the second connection element and the second partial region of the second connection element are connected to one another; the second semiconductor chip is arranged on the first partial region of the second connection element; the first partial region of the first connection element and the first partial region of the second connection element are arranged alongside one another along a first main extension direction of the carrier; the third connection element and the second partial region of the second connection element are arranged alongside one another along the first main extension direction; and the third connection element and the first partial region of the second connection element are arranged alongside one another along a second main extension direction, which runs transversely with respect to the first main extension direction, of the carrier.

19 . The surface-mountable multi-chip component according to claim 17 , wherein the first and second semiconductor chips each have a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, wherein semiconductor regions of the same conductivity type of the first and second semiconductor chips are electrically connected to one another by the second connection element.

20 . The surface-mountable multi-chip component according to claim 19 , wherein semiconductor regions of the first and second semiconductor chips that adjoin the connection elements are of different conductivity types.

21 . The surface-mountable multi-chip component according to claim 17 , wherein a first partial region of the first connection element and a first partial region of the second connection element are arranged alongside one another along a first main extension direction of the carrier.

22 . The surface-mountable multi-chip component according to claim 17 , wherein the third connection element and a second partial region of the second connection element are arranged alongside one another along a first main extension direction of the carrier.

23 . The surface-mountable multi-chip component according to claim 17 , wherein the third connection element and a first partial region of the second connection element are arranged alongside one another along a second main extension direction of the carrier.

24 . The surface-mountable multi-chip component according to claim 17 , wherein no semiconductor chip is arranged on the third connection element.

25 . The surface-mountable multi-chip component according to claim 17 , wherein the first semiconductor chip is electrically connected to the second connection element by an electrical conductor.

26 . The surface-mountable multi-chip component according to claim 25 , wherein the second semiconductor chip is electrically connected to the third connection element by an electrical conductor.

27 . The surface-mountable multi-chip component according to claim 17 , wherein the carrier further comprises a main body, wherein the first, second and third connection elements are at least partly embedded in the main body.

28 . The surface-mountable multi-chip component according to claim 27 , wherein the second connection element is partly covered by the main body at a rear-side main surface of the carrier.

29 . The surface-mountable multi-chip component according to claim 17 , wherein the first and second semiconductor chips are separated from one another by an interspace having a lateral dimension of greater than zero and at most 0.1 mm.

30 . The surface-mountable multi-chip component according to claim 17 , wherein the first and second semiconductor chips each have a radiation-transmissive covering element arranged at a front-side surface of the first and second semiconductor chips facing away from the respective connection element.

31 . The surface-mountable multi-chip component according to claim 17 , further comprising a housing frame, wherein the first and second semiconductor chips are arranged within the housing frame.

32 . The surface-mountable multi-chip component according to claim 17 , wherein the first and second semiconductor chips emit radiation in different wavelength ranges during operation.

33 . The surface-mountable multi-chip component according to claim 17 , wherein the separate first and third electrodes semiconductor chips are separately drivable from one another by means of the common cathode or anode.

34 . A surface-mountable multi-chip component comprising:
a carrier having a main body, a first connection element, a second connection element and third connection element, the first, second and third connection elements being at least partially embedded in the main body and being electrically insulated from one another, wherein the second connection element is partly covered by the main body at a rear-side main surface of the carrier; a first semiconductor chip arranged on the first connection element and electrically connected to the first and second connection elements, wherein the first connection element forms a first electrode and the second connection element forms a second electrode for the first semiconductor chip; and a second semiconductor chip arranged on the second connection element and electrically connected to the second and third connection elements, wherein the third connection element forms a first electrode and the second connection element forms a second electrode for the second semiconductor chip, and wherein the second connection element forms a common cathode or anode for the first and second semiconductor chips during operation.

35 . A surface-mountable multi-chip component comprising:
a carrier having a first connection element, a second connection element and third connection element that are electrically insulated from one another; a first semiconductor chip arranged on the first connection element and electrically connected to the first and second connection elements, wherein the first connection element forms a first electrode and the second connection element forms a second electrode for the first semiconductor chip; and a second semiconductor chip arranged on the second connection element and electrically connected to the second and third connection elements, wherein the third connection element forms a fir

Assignees

• Osram Opto Semiconductors Gmbh

Inventors

• Morgott Stefan

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W90/00 Primary

  Package configurations · CPC title