Dual work function integration for stacked finfet

Patent metadata

Field	Value
Publication number	US-2016336235-A1
Application number	US-201615149360-A
Country	US
Kind code	A1
Filing date	May 9, 2016
Priority date	May 11, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked fin CMOS device includes a fin stack having a first semiconductor fin over a substrate, a dielectric fin atop the first semiconductor fin and a second semiconductor fin atop the dielectric fin, and a gate sack straddling the fin stack. The gate stack includes a first metal gate portion surrounding a channel portion of the first semiconductor fin and a second metal gate portion surrounding a channel portion of the second semiconductor fin. The first metal gate portion has a fist work function suitable to reduce a threshold voltage of a field effect transistor (FET) of a first conductivity type, while the second gate portion has a second work function suitable to reduce a threshold voltage of a FET of a second conductivity type opposite the first conductivity type.

First claim

What is claimed is:

1 . A method of forming a semiconductor structure comprising:
forming a gate cavity laterally surrounded by an interlevel dielectric (ILD) layer, the gate cavity exposing a portion of at least one fin stack comprising a first semiconductor fin, a dielectric fin atop the first semiconductor fin, and a second semiconductor fin atop the dielectric fin; forming a stack in the gate cavity, the stack comprising a gate dielectric located over sidewalls and a bottom surface of the gate cavity, a first work function metal located over the gate dielectric, and a first gate conductor layer portion located over the first work function metal and filling a remaining volume of the gate cavity; recessing the first gate conductor layer portion to provide a first gate conductor, wherein a top surface of the first gate conductor is located between a top surface of the dielectric fin and a bottom surface of the dielectric fin; forming a second work function metal layer on a portion of the first work function metal that is not covered by the first gate conductor and on a top surface of the first gate conductor; and forming a second gate conductor layer on the second work function metal layer to fill the gate cavity.

2 . The method of claim 1 , wherein the forming the gate cavity comprises:
forming the at least one fin stack on a substrate; forming a sacrificial gate stack straddling the portion of the at least one fin stack; forming the ILD layer laterally surrounding the sacrificial gate stack; and removing the sacrificial gate stack to provide the gate cavity.

3 . The method of claim 2 , further comprising forming a gate spacer on each sidewall of the sacrificial gate sack prior to the forming the ILD layer.

4 . The method of claim 3 , further comprising forming first source/drain regions in portions of the first semiconductor fin that are exposed by the sacrificial gate stack, and second source/drain regions in portions of the second semiconductor fin that are exposed by the sacrificial gate stack prior to the forming the ILD layer.

5 . The method of claim 4 , wherein the forming the first source/drain regions comprises implanting dopants of a first conductivity to the exposed portions of the first semiconductor fin, and the forming the second source/drain regions comprises implanting dopants of a second conductivity opposite to the first conductivity to the exposed portions of the second semiconductor fin.

6 . The method of claim 5 , further comprising forming the stack in the gate stack, subsequent to the forming of each of the first source/drain regions and the second source/drain regions, wherein topmost surfaces of each of the gate dielectric, the first work function metal, and the first gate conductor portion are coplanar with a topmost surface of the ILD layer.

7 . The method of claim 3 , further comprising forming a contact structure connecting one of the first source/drain regions to one of the second source/drain regions.

8 . The method of claim 1 , wherein the first gate conductor and the lower portion of the first work function metal surround a lower portion of the portion of the dielectric fin, and the remaining portion of the first work function metal, the second work function metal and the second gate conductor surrounds a remaining portion of the portion of the dielectric fin.

9 . The method of claim 1 , further comprising removing the exposed portion of the first work function metal that is not covered by the first gate conductor to expose an upper portion of the gate dielectric, wherein the second work function metal layer is in contact with the upper portion of the gate dielectric.

10 . The method of claim 9 , wherein each portion of the remaining first work function metal and the first gate conductor has a top surface located below a top surface of the dielectric fin and a bottom surface of the dielectric fin.

11 . The method of claim 10 , wherein a topmost surface of the first gate conductor is coplanar with a topmost surface of the portion of the remaining first work function metal.

12 . The method of claim 9 , wherein topmost surfaces of each of the gate dielectric, the second work function metal and the second gate conductor are coplanar with a topmost surface of an ILD layer that laterally surrounds the second work function metal and the second gate conductor.

13 . The method of claim 1 , wherein the first work function metal has a first work function, and the second work function metal has a second work function different from the first work function.

14 . The method of claim 13 , wherein one of the first work function metal and the second work function metal comprises TiAlC, TaAlC, TiAl, Ti or Al, and another of the first work function metal and the second work function metal comprises TiN, TaN, NbN, VN, or WN.

15 . The method of claim 13 , wherein one of the first work function and the second work function ranges from 4.1 eV to 4.3 eV, and another of the first work function and the second work function ranges from 4.5 eV to 5.2 eV.

16 . The method of claim 1 , wherein the first semiconductor fin comprises a silicon material, and the second semiconductor fin comprises a silicon germanium material.

17 . The method of claim 1 , wherein the dielectric fin comprises silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10D88/01

  Manufacture or treatment · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D84/853

  comprising FinFETs · CPC title