Apparatus, system, and method for handling aligned wafer pairs

US2016336208A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016336208-A1
Application numberUS-201615150856-A
CountryUS
Kind codeA1
Filing dateMay 10, 2016
Priority dateMay 15, 2015
Publication dateNov 17, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding applications includes an end effector having a frame member and a floating carrier connected to the frame member with a gap formed therebetween, wherein the floating carrier has a semi-circular interior perimeter. The centered semiconductor wafer pairs are positionable within a processing system using the end effector under robotic control. The centered semiconductor wafer pairs are bonded together without the presence of the end effector in the bonding device.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of placing aligned wafers into a bonding device, the method comprising: securing wafers in spaced alignment with an end effector having a frame member and a floating carrier movably connected to the frame member; using a robot to move the end effector, thereby moving the wafers into a bonding chamber of a bonder; unloading the wafers from the end effector; removing the end effector from the bonding chamber; and bonding the wafers. 2 . The method of claim 1 , wherein the wafers are secured in spaced alignment using a plurality of clamp-spacer assemblies connected to at least one of the frame member and floating carrier. 3 . The method of claim 2 , wherein the plurality of clamp-spacer assemblies are spaced substantially equidistantly on a semi-circular interior perimeter of the floating carrier. 4 . The method of claim 1 , wherein unloading the wafers from the end effector further comprises decoupling the floating carrier from the frame member. 5 . The method of claim 1 , wherein unloading the wafers from the end effector further comprises: inserting at least one bonder spacer flag between the wafers; and removing at least one end effector spacer flag from between the wafers. 6 . The method of claim 1 , wherein securing wafers in spaced alignment with the end effector further comprises retaining the wafers with a plurality of vacuum pads connected to the floating carrier, wherein each of the plurality of vacuum pads extend inward of a semi-circular interior perimeter of the floating carrier. 7 . The method of claim 6 , further comprising adjusting a position of the plurality of vacuum pads on the floating carrier radially along the semi-circular interior perimeter. 8 . The method of claim 6 , further comprising adjusting the floating carrier relative to the frame member along an axis of the semi-circular interior perimeter, wherein a size of a gap between the floating carrier and the frame member is adjustable. 9 . The method of claim 1 , further comprising centering the floating carrier to the frame member with a centering mechanism removably engagable between the frame member and the floating carrier, wherein the centering mechanism prevents a position change of the floating carrier relative to the frame member. 10 . The method of claim 1 , wherein unloading the wafers from the end effector further comprises: contacting a chuck of the bonder to at least one of the wafers; applying a compression force to the wafers with a compression pin; inserting at least one bonder spacer flag between the wafers; removing an end effector clamp from the wafers; and removing an end effector spacer flag from between the wafers. 11 . The method of claim 10 , wherein applying the compression force to the wafers with the compression pin further comprises matching a compression pressure between upper and lower chucks of the bonder. 12 . The method of claim 10 , wherein the compression pin further comprises at least two compression pins. 13 . The method of claim 10 , further comprising substantially matching a temperature of the compression pin with a temperature of the upper chuck of the bonder. 14 . The method of claim 1 , wherein bonding the wafers further comprises bonding the wafers in spaced alignment without contact of the wafers with the end effector during a bonding process. 15 . A method for placing aligned wafer pairs into a processing device, the method comprising: carrying wafers in spaced alignment with an end effector having a frame member and a floating carrier, wherein the floating carrier is movably connected to the frame member; changing a location of the end effector with a robotic arm connected to the end effector; and placing the wafers in spaced alignment into a processing chamber of a processing device by decoupling the floating carrier from the frame member while the frame member and floating carrier are positioned within the processing chamber. 16 . The method of claim 15 , wherein placing into the processing chamber further comprises: contacting a chuck of the processing device with at least one of the wafers; applying a compression force to the wafers with a compression pin; inserting at least one bonder spacer flag between the wafers; removing an end effector clamp from the wafers; and removing an end effector spacer flag from between the wafers. 17 . The method of claim 15 , wherein applying the compression force to the wafers with the compression pin further comprises matching a compression pressure between upper and lower chucks of the processing device. 18 . The method of claim 15 , further comprising substantially matching a temperature of the compression pin with a temperature of the upper chuck of the bonder. 19 . The method of claim 15 , wherein applying the compression force to the wafers with the compression pin further comprises applying pressure with at least two compression pins, wherein at least one of the at least two compression pins applies a pressure at a substantial center point of the wafers and at least one of the at least two compression pins applies a pressure offset from the substantial center point of the wafers. 20 . A method of transporting aligned wafers with an end effector, the method comprising: holding at least two aligned wafers with a plurality of vacuum pads connected to a floating carrier of the end effector, wherein the floating carrier is connected to a frame member with a gap formed therebetween, and wherein the floating carrier has a semi-circular interior perimeter with each of the plurality of vacuum pads extending inward of the semi-circular interior perimeter of the floating carrier; and moving the end effector with a robotic arm.

Assignees

Inventors

Classifications

  • batch processes · CPC title

  • Means for moving chips, wafers or other parts, e.g. conveyor belts · CPC title

  • Means for applying energy, e.g. ovens or lasers · CPC title

  • Means for controlling the bonding environment, e.g. valves or vacuum pumps · CPC title

  • Bonding techniques, e.g. hybrid bonding · CPC title

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What does patent US2016336208A1 cover?
An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding applications includes an end effector having a frame member and a floating carrier connected to the frame member with a gap formed therebetween, wherein the floating carrier has a semi-circular interior perimeter. The centered semiconduc…
Who is the assignee on this patent?
Suss Microtec Lithography Gmbh
What technology area does this patent fall under?
Primary CPC classification H10P72/3302. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Nov 17 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).