Method and apparatus for processing data by using memory

Patent metadata

Field	Value
Publication number	US-2016335028-A1
Application number	US-201415112780-A
Country	US
Kind code	A1
Filing date	Jul 18, 2014
Priority date	Jan 20, 2014
Publication date	Nov 17, 2016
Grant date	—

Abstract

Provided is a data processing apparatus including: a pipeline including a plurality of stages; and a memory that stores data that is processed in the pipeline.

First claim

1 . A data processing apparatus comprising:
a pipeline including a plurality of stages; and a memory that stores data that is processed in the pipeline.

2 . The data processing apparatus of claim 1 , wherein the memory comprises a multi-bank static random access memory (SRAM) that includes a plurality of banks, and the data is split and stored in the plurality of banks.

3 . The data processing apparatus of claim 2 , wherein each of the plurality of banks comprises one read port and one write port, and
when different stages of the pipeline simultaneously perform read operations or write operations with respect to a same bank, data about the read operations or the write operations is stored in a plurality of different banks.

4 . The data processing apparatus of claim 3 , wherein when the different stages of the pipeline simultaneously perform two write operations to the same bank, the different stages of the pipeline write one of two pieces of write data to the same bank and the other piece to an additional bank.

5 . The data processing apparatus of claim 3 , wherein when the different stages of the pipeline simultaneously perform two read operations with respect to the same bank, the different stages of the pipeline read data stored in the same bank and an additional bank.

6 . The data processing apparatus of claim 2 , wherein each of the plurality of banks includes R read ports and W write ports, and
different stages of the pipeline simultaneously perform R or less read operations or W or less write operations with respect to the same bank.

7 . The data processing apparatus of claim 6 , wherein when the different stages of the pipeline simultaneously perform write operations that exceed W, to the same bank, the different stages of the pipeline perform W write operations to the same bank, and perform the rest of the write operations to additional banks.

8 . The data processing apparatus of claim 6 , wherein when the different stages of the pipeline simultaneously perform read operations that exceed R with respect to the same bank, the different stages of the pipeline read R pieces of data stored in the same bank and the rest of data that exceed R, stored in the additional banks.

9 . The data processing apparatus of claim 1 , wherein the pipeline performs ray tracing by using ray data, and
the memory stores the ray data by splitting the ray data.

10 . The data processing apparatus of claim 1 , further comprising a plurality of launchers that schedule data to be processed by the different stages.

11 . A data processing method performed by using a pipeline including a plurality of stages, the data processing method comprising:
storing data processed in the pipeline, in a memory; and processing data by using the data stored in the memory.

12 . The data processing method of claim 11 , wherein the memory is a multi-bank static random access memory (SRAM) including a plurality of banks, and the data is split and stored in the plurality of banks.

13 . The data processing method of claim 12 , wherein each of the plurality of banks comprises one read port and one write port, and
in the storing of the data, when different stages of the pipeline simultaneously perform read operations or write operations with respect to the same bank, data about the read operations or the write operations is assigned to a plurality of different banks.

14 . The data processing method of claim 13 , wherein the storing comprises:
assigning an additional bank when the different stages of the pipeline simultaneously perform two write operations to the same bank; and storing data about one of the two write operations in the same bank and data about the other write operation to the additional bank.

15 . The data processing method of claim 13 , wherein the storing comprises:
assigning an additional bank when the different stages of the pipeline simultaneously perform two read operations with respect to the same bank; and copying data about one of the read operations and storing the data in the additional bank.

16 . The data processing method of claim 12 , wherein the multi-bank SRAM comprises R read ports and W write ports, and
in the storing of data, R or less read operations or W or less write operations with respect to the same bank that are simultaneously performed by using different stages of the pipeline are stored in the same bank.

17 . The data processing method of claim 16 , the storing comprises:
when the different stages of the pipeline simultaneously perform write operations that exceed W to the same bank, assigning additional banks according to the number of the write operations that exceed W; and writing data about W write operations to the same bank, and data about the rest of the write operations to the additional banks.

18 . The data processing method of claim 16 , wherein the storing of data comprises:
when the different stages of the pipeline simultaneously perform read operations that exceed R, assigning additional banks according to the number of read operations that exceed R; and copying data about the rest of read operations that exceed R and storing the data in the additional banks.

19 . The data processing method of claim 11 , wherein the pipeline performs ray tracing by using ray data, and
the memory stores the ray data by splitting the ray data.

20 . The data processing method of claim 11 , further comprising scheduling data to be processed by the stages,
wherein the processing of data comprises processing data according to the scheduling.

21 . A recording medium having embodied thereon a program for executing the method of claim 11 .

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Mookyoung
• Ryu Soojung
• Shin Youngsam
• Lee Wonjong

Classifications

• G06T2200/28

  involving image processing hardware · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06T15/06

  Ray-tracing · CPC title

• G06T1/60

  Memory management · CPC title

• G06F1/20

  Cooling means · CPC title