Multi-step incremental switching scheme

Patent metadata

Field	Value
Publication number	US-2016334902-A1
Application number	US-201514870243-A
Country	US
Kind code	A1
Filing date	Sep 30, 2015
Priority date	May 15, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

A capacitance measurement circuit cancels background capacitance while reducing charge leakage and supply ripples during reset phases and integrate phases. The capacitance measurement circuit operates a first switch into a linear mode causing a first resistance in the first switch, and after a delay, operates a second switch into a saturation mode causing a second resistance in parallel to the first resistance.

First claim

What is claimed is:

1 . A processing system for a capacitive sensing device, the processing system comprising:
a capacitance measurement circuit configured to be coupled to a sensor electrode for measuring capacitance from the sensor electrode, the capacitance measurement circuit comprising:
a differential amplifier having a first input coupled to the sensor electrode, a second input, and an output,
a feedback capacitor coupled between the first input of the differential amplifier and the output of the differential amplifier, and
a first switch and a second switch coupled between the feedback capacitor and the output of the differential amplifier in series; and
a control module configured to:
turn on the first switch and apply a first resistance in series with the feedback capacitor, and
after a time delay, turn on the second switch and placing a second resistance in parallel with the first resistance, which lowers a total resistance in series with the feedback capacitor.

2 . The processing system of claim 1 , wherein the first resistance in series with the feedback capacitor is greater than the second resistance.

3 . The processing system of claim 1 , wherein the first switch and the second switch comprise transistors having a source terminal, a drain terminal, and a gate terminal, wherein the source terminals of the first and second switches are connected in parallel, and the drain terminals of the first and second switches are connected in parallel; and
wherein the control module is configured to apply different control signals to the gate terminals of the first and second switches.

4 . The processing system of claim 1 , wherein turning on the first switch and applying the first resistance in series with the feedback capacitor increases a settling response of the capacitance measurement circuit, and
wherein turning on the second switch and placing the second resistance in parallel with the first resistance decreases the settling response of the capacitance measurement circuit.

5 . The processing system of claim 1 , wherein the feedback capacitor is a first feedback capacitor, and the capacitance measurement circuit further comprises a second feedback capacitor in parallel with the first feedback capacitor and a third switch.

6 . The processing system of claim 1 , wherein the capacitance measurement circuit further comprises a third switch operably to connect the feedback capacitor to a voltage level during a reset phase and pre-charge the feedback capacitor to cancel background capacitance.

7 . The processing system of claim 1 , wherein turning on the first switch and applying the first resistance in series with the feedback capacitor reduces charge leakage in the feedback capacitor when switching from a reset phase to an integrate phase.

8 . A processing system for a capacitive sensing device, the processing system comprising:
a capacitance measurement circuit configured to be coupled to a sensor electrode for measuring capacitance from the sensor electrode, the capacitance measurement circuit comprising:
a differential amplifier having a first input coupled to the sensor electrode, a second input, and an output,
a first feedback capacitance coupled between the first input of the differential amplifier and the output of the differential amplifier,
a second feedback capacitance coupled in parallel to the first feedback capacitance, the second feedback capacitance comprising a plurality of capacitors in series with a plurality of associated switches; and
a control module configured to, during an integrate phase, control each switch of the plurality of switches to couple the associated capacitor to the output of the differential amplifier after a sequential delay.

9 . The processing system of claim 8 , wherein the plurality of capacitors comprising the second feedback capacitance are arranged in parallel.

10 . The processing system of claim 8 , wherein the control module is configured to determine the sequential delay based a counter.

11 . The processing system of claim 8 , wherein the control module configured to, during the integrate phase, control each switch of the plurality of switches is further configured to:
close a first switch associated with a first capacitor of the plurality of capacitors to couple the first capacitor between the first input and the output of the differential amplifier, and close a second switch associated with a second capacitor of the plurality of capacitors to couple the second capacitor between the first input and the output of the differential amplifier and in parallel with the first capacitor and the first feedback capacitance.

12 . The processing system of claim 8 , wherein the plurality of capacitors of the second feedback capacitance are arranged in subsets, wherein each subset is switched on at a same time during an integrate phase.

13 . The processing system of claim 8 , wherein the second feedback capacitance further comprises a plurality of pre-charge switches coupled in parallel to the plurality of switches, wherein each pre-charge switch is operably to connect the associated capacitor to a voltage level during a reset phase and pre-charge the associated capacitor to cancel background capacitance.

14 . The processing system of claim 8 , wherein controlling each switch of the plurality of switches to couple the associated capacitor to the output of the differential amplifier after the sequential delay reduces charge leakage in the first feedback capacitance when switching from a reset phase to an integrate phase.

15 . A method of capacitance measurement, the method comprising:
resetting a feedback capacitor of a capacitance measurement circuit to a first voltage level, wherein the feedback capacitor is coupled between a first input of a differential amplifier and an output of the differential amplifier; opening a plurality of switches between the feedback capacitor and the output of the differential amplifier; coupling a sensor electrode and the first input of the differential amplifier to initiate a measurement phase; closing a first switch of the plurality of switches between the feedback capacitor and the output of the differential amplifier; closing a remainder of the plurality of switches after a delay from closing the first switch; and operating the differential amplifier to integrate charge on the sensor electrode, such that an absolute capacitance corresponding to a coupling between the sensor electrode and an input object is measured.

16 . The method of claim 15 , wherein resetting the feedback capacitor of the capacitance measurement circuit to the first voltage level further comprises:
operating a pre-charge switch to couple the feedback capacitor to a second voltage level and pre-charge the feedback capacitor for background capacitance cancellation.

17 . The method of claim 15 , wherein the plurality of switches between the feedback capacitor and the output of the differential amplifier comprises:
a first transistor and a second transistor having a first, second, and third terminals, wherein the first terminals of the first and second switches are connected in parallel, and the second terminals of the first and second switches are connected in parallel, wherein the first and second transistors are configured to receive control signals on the third terminals of the first and second transistors.

18 . The method of claim 15 , wherein closing the first switch of the plurality of switches between the feedback capacitor and the output of the dif

Assignees

• Synaptics Inc

Inventors

• Li Zheming
• Ganta Saikrishna
• Chung Tae-Song
• Betancourt Rafael
• Weinerth John Michael
• Shahrokhi Farzaneh

Classifications

• H03K2217/96074

  Switched capacitor · CPC title

• G06F2203/04108

  Touchless 2D- digitiser, i.e. digitiser detecting the X/Y position of the input means, finger or stylus, also when it does not touch, but is proximate to the digitiser's interaction surface without distance measurement in the Z direction · CPC title

• G06F3/044 Primary

  by capacitive means · CPC title

• G06F3/016

  Input arrangements with force or tactile feedback as computer generated output to the user · CPC title

• G06F3/0416

  Control or interface arrangements specially adapted for digitisers · CPC title