Display device with reduced manufacturing cost and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016334679-A1
Application number	US-201615040243-A
Country	US
Kind code	A1
Filing date	Feb 10, 2016
Priority date	May 12, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

A display device includes a gate line and a data line on a first substrate. A first passivation layer disposed thereon has a first contact hole. A second passivation layer on the first passivation layer has a second contact hole. A common electrode is disposed on the second passivation layer and a residual pattern is disposed on a drain electrode. A third passivation layer, having a third contact hole, is disposed on the common electrode. A pixel electrode, connected to the drain electrode, is disposed on the third passivation layer. A groove is defined between the first and second passivation layers. The common electrode has a open circuit from the residual pattern thereof.

First claim

What is claimed is:

1 . A display device comprising:
a first substrate; a gate line and a data line disposed on the first substrate; a first passivation layer disposed on both the gate line and the data line, the first passivation layer having a first contact hole; a second passivation layer disposed on the first passivation layer, the second passivation layer having a second contact hole; a common electrode and a residual pattern of the common electrode, the common electrode being disposed on the second passivation layer and the residual pattern of the common electrode being disposed on a drain electrode; a third passivation layer disposed on the common electrode, the third passivation layer having a third contact hole; and a pixel electrode disposed on the third passivation layer, the pixel electrode being connected to the drain electrode, wherein a groove is defined between the first passivation layer and the second passivation layer, and the common electrode includes an open circuit resulting from the residual pattern of the common electrode.

2 . The display device of claim 1 , wherein the groove is larger in the second passivation layer than in the first passivation layer.

3 . The display device of claim 2 , further comprising a thin film transistor connected to both the gate line and the data line.

4 . The display device of claim 3 , wherein the pixel electrode is connected to the thin film transistor.

5 . The display device of claim 4 , wherein the pixel electrode has a plurality of cut-out portions, and the common electrode has a planar shape.

6 . The display device of claim 5 , further comprising a second substrate aligned with the first substrate.

7 . A method of manufacturing a display device, the method comprising:
forming a gate line and a data line on a first substrate; forming a first passivation layer on both the gate line and the data line; forming a second passivation layer on the first passivation layer; etching the first passivation layer and the second passivation layer to thereby define a groove between the first passivation layer and the second passivation layer; and coating a common electrode over an entire surface of the first substrate.

8 . The method of claim 7 , wherein the forming of the first passivation layer comprises forming a plurality of thin film layers each deposited under different temperature and pressure conditions.

9 . The method of claim 8 , wherein the forming of the first passivation layer further comprises depositing a thin film layer at a higher pressure in a final step than in a previous step.

10 . The method of claim 9 , further comprising forming a third passivation layer on the common electrode.

11 . The method of claim 10 , wherein the groove is generated using a dry-etching method.

12 . The method of claim 11 , further comprising forming a pixel electrode on the third passivation layer.

13 . The method of claim 12 , further comprising forming a thin film transistor connected to both the gate line and the data line.

14 . The method of claim 13 , wherein the pixel electrode has a plurality of cut-out portions, and the common electrode has a planar shape.

15 . The method of claim 14 , further comprising forming a second substrate aligned with the first substrate.

16 . A display device, comprising:
a first substrate; a gate line and a data line disposed on the first substrate; a first passivation layer comprising a first thin film layer having a first density and at least one second thin film layer having a second density different from the first density, the first passivation layer disposed on both the gate line and the data line and having a first contact hole; a second passivation layer disposed on the first passivation layer, the second passivation layer having a second contact hole; a common electrode disposed on the second passivation layer; a third passivation layer disposed on the common electrode, the third passivation layer having a third contact hole; and a pixel electrode disposed on the third passivation layer, the pixel electrode connected to the drain electrode, wherein a groove is defined between the first passivation layer and the second passivation layer.

17 . The display device of claim 16 , wherein the groove is larger in the second passivation layer than in the first passivation layer.

18 . The display device of claim 16 , further comprising a thin film transistor connected to both the gate line and the data line.

19 . The display device of claim 16 , further comprising a pixel electrode, having a plurality of cut-out portions, connected to a thin film transistor.

20 . The display device of claim 16 , wherein the common electrode has a planar shape.

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Jaeho
• Koo Bonyong

Classifications

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G02F1/13439

  characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title

• G02F1/134309 Primary

  characterised by their geometrical arrangement · CPC title