Recess with Tapered Sidewalls for Hermetic Seal in MEMS Devices

Patent metadata

Field	Value
Publication number	US-2016332867-A1
Application number	US-201514713287-A
Country	US
Kind code	A1
Filing date	May 15, 2015
Priority date	May 15, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

An integrated circuit (IC) device is provided. The IC device includes a first substrate having a frontside and a backside. The backside includes a first cavity extending into the first substrate. A dielectric layer is disposed on the backside of the first substrate, and includes an opening corresponding to the first cavity and a trench extending laterally away from the opening and terminating at a gas inlet recess. A recess in the frontside of the first substrate extends downwardly from the frontside to the dielectric layer. The recess has substantially vertical upper sidewalls which adjoin lower sidewalls which taper inwardly from the substantially vertical sidewalls to points on the dielectric layer which circumscribe the gas inlet recess. A conformal sealant layer is arranged over the frontside of the first substrate, along the substantially vertical upper sidewalls, and along the lower sidewalls. The sealant layer hermetically seals the gas inlet recess.

First claim

1 . An integrated circuit (IC) device including:
a first substrate having a frontside and a backside, wherein the backside includes a first cavity extending into the first substrate; a dielectric layer disposed on the backside of the first substrate, wherein the dielectric layer includes an opening corresponding to the first cavity and a trench extending laterally away from the opening and terminating at a gas inlet recess; a recess in the frontside of the first substrate extending downwardly from the frontside to the dielectric layer, the recess having substantially vertical upper sidewalls which adjoin lower sidewalls which taper inwardly from the substantially vertical sidewalls to points on the dielectric layer which circumscribe the gas inlet recess; and a conformal sealant layer over the frontside of the first substrate and along the substantially vertical upper sidewalls, along the lower sidewalls, the conformal sealant layer establishing a plug that hermetically seals the first cavity at the gas recess inlet.

2 . The IC device of claim 1 , wherein the first cavity retains a first pressure and wherein the backside of the first substrate further comprises:
a second cavity extending into the first substrate, wherein the second cavity retains a second pressure that differs from a first pressure retained in the first cavity, wherein the second cavity is isolated from the first cavity without a gas inlet recess in the frontside of the first substrate facilitating access to the second cavity.

3 . The IC device of claim 1 ,
wherein a substantially vertical upper sidewall lies on a first plane that meets the frontside of the first substrate at a first angle ranging between eighty-seven-degrees and ninety-three degrees; and wherein a lower sidewall lies on a second plane that meets the frontside of the first substrate at a second angle ranging between sixty-degrees and eighty-eight-degrees.

4 . The IC device of claim 1 , further comprising:
upper tapered sidewalls that taper outwardly from upper portions of the substantially vertical sidewalls nearest the frontside of the first substrate.

5 . The IC device of claim 4 ,
wherein a substantially vertical sidewall lies on a first plane that meets the frontside of the first substrate at a first angle ranging between eighty-seven-degrees and ninety-three degrees; wherein a lower sidewall lies on a second plane that meets the frontside of the first substrate at a second angle ranging between sixty-degrees and eighty-eight-degrees; and wherein an upper tapered sidewall lies on a third plane that meets the frontside of the first substrate at a third angle ranging between sixty-degrees and eighty-eight-degrees.

6 . The IC device of claim 5 , wherein the second and third angles are different.

7 . The IC device of claim 5 , wherein the second and third angles equal.

8 . The IC device of claim 1 ,
wherein a height of a substantially vertical sidewall measured between the frontside of the first substrate and a point where the substantially vertical sidewall adjoins a tapered sidewall ranges between 30 micrometers and 200 micrometers, and wherein a height of the tapered sidewall as measured between the point and the backside of the first substrate ranges between 10 micrometers and 50 micrometers.

9 . The IC device of claim 1 :
wherein the conformal sealant layer is a conformal oxide layer, and further comprising: a conformal aluminum layer disposed in the recess over the conformal oxide layer.

10 . The IC device of claim 1 , further comprising:
a second substrate bonded to a backside of the dielectric layer on the first substrate such that a frontside of the second substrate covers the gas inlet recess and such that a MEMS device region of the second substrate is aligned with the first cavity; and a third substrate bonded to a backside of the second substrate, wherein the third substrate includes a third cavity aligned to the MEMS region.

11 . A device, comprising:
a CMOS die including a CMOS substrate; a MEMS die including a MEMS substrate and bonded to the CMOS die; a cap structure including a cap substrate and a dielectric layer on an underside of the cap structure, wherein the dielectric layer includes first and second cavities and a gas inlet recess extending laterally from the first cavity, the dielectric layer of the cap structure bonded to an upper surface of the MEMS die; a recess having substantially vertical sidewalls which extend downwardly from an upper surface of the cap structure over the gas inlet recess and which meet lower sidewalls which taper inwardly from the substantially vertical sidewalls, wherein the lower sidewalls extend downwardly to an upper surface of the dielectric layer; and a conformal oxide layer over the upper surface of the cap structure, along the substantially vertical sidewalls, and along the lower sidewalls, wherein the conformal oxide layer spans the gas inlet recess and seals the first cavity at a first predetermined pressure, which is different from a second predetermined pressure retained in the second cavity.

12 . The device of claim 11 , wherein the recess includes:
a lower tapered sidewall that tapers inwardly from a lower portion of a substantially vertical sidewall; and an upper tapered sidewall that flares outwardly from an upper portion of the substantially vertical sidewall.

13 . A method of forming an IC (integrated circuit) device, the method comprising:
receiving a first wafer having a frontside and a backside, wherein a dielectric layer is disposed on the backside of the first wafer; forming a gas inlet recess in the dielectric layer; forming first and second cavity recesses, which extend through the dielectric layer and into the first wafer, wherein the first cavity recess is formed to adjoin the gas inlet recess and the second cavity recess is isolated from the gas inlet recess; receiving a second wafer having a frontside and a backside; bonding the frontside of the second wafer to the backside of the first wafer such that first and second MEMS device regions of the second wafer are aligned to the first and second cavity recesses, respectively; after the first and second wafers have been bonded together, performing a Bosch etch into the frontside of the first wafer to form a recess over the gas inlet recess, wherein the recess exhibits a lower surface terminating within the first wafer over the gas inlet recess and exhibits substantially vertical sidewalls disposed on opposite sides of the gas inlet recess; and performing a tapering etch to increase a depth of the recess and to expose the gas inlet recess, wherein the tapering etch results in lower recess sidewalls that taper inwardly from the substantially vertical sidewalls to points on the dielectric layer which are on opposite sides of the gas inlet recess.

14 . The method of claim 13 , further comprising:
forming a conformal layer over the frontside of the first wafer, along the substantially vertical sidewalls, and along the lower sidewalls to hermetically seal the gas inlet recess and thereby seal the first cavity.

15 . The method of claim 14 , wherein bonding the first and second wafers seals both the first and second cavities at an initial pressure, and wherein forming the conformal layer re-seals the first cavity at a subsequent pressure different from the initial pressure while the second cavity remains at the initial pressure.

16 . The method of claim 14 , further comprising:
bonding a third wafer to a backside of the second wafer, wherein the third wafer includes a cavity recess whic

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tseng Lee-Chuan
• Wu Chang-Ming
• Liu Shih-Chang

Classifications

• B81C2201/0112

  Bosch process · CPC title

• B81C1/00293 Primary

  maintaining a controlled atmosphere with processes not provided for in B81C1/00285 · CPC title

• B81B2201/0235

  Accelerometers · CPC title

• B81B7/0041 Primary

  maintaining a controlled atmosphere with techniques not provided for in B81B7/0038 · CPC title

• B81C2203/0145

  Hermetically sealing an opening in the lid · CPC title