Transmission channel for ultrasound applications

Patent metadata

Field	Value
Publication number	US-2016332196-A1
Application number	US-201615220208-A
Country	US
Kind code	A1
Filing date	Jul 26, 2016
Priority date	Dec 17, 2014
Publication date	Nov 17, 2016
Grant date	—

Abstract

A transmission channel transmits high-voltage pulses in a transmission phase and receives echoes of the high-voltage pulses in a receiving phase. The transmission channel includes a buffer with anti-memory circuitry to couple drain conduction terminals of buffer transistors of a high-side of a buffer of the transmission channel to a low-side reference voltage of a low-side of the buffer and couple drain conduction terminals of buffer transistors of the low-side of the buffer to a high-side reference voltage of the high-side of the buffer during the clamping phase.

First claim

1 . A method, comprising:
transmitting high-voltage pulses through a transmission channel in a transmission phase; coupling drain conduction terminals of buffer transistors of a high-side of a buffer of the transmission channel to a low-side reference voltage of a low-side of the buffer during a clamping phase; and coupling drain conduction terminals of buffer transistors of the low-side of the buffer to a high-side reference voltage of the high-side of the buffer during the clamping phase.

2 . The method of claim 1 , comprising:
coupling the drain conduction terminals of the buffer transistors of the high-side of the buffer to the low-side reference voltage during a receiving phase; and coupling the drain conduction terminals of the buffer transistors of the low-side of the buffer to the high-side reference voltage during the receiving phase.

3 . The method of claim 2 , comprising:
coupling the drain conduction terminals of the buffer transistors of the high-side of the buffer to the low-side reference voltage when a low-side buffer transistor is on; and coupling the drain conduction terminals of the buffer transistors of the low-side of the buffer to the high-side reference voltage when a high-side buffer transistor is on.

4 . The method of claim 1 , comprising:
coupling the drain conduction terminals of the buffer transistors of the high-side of the buffer to the low-side reference voltage when a low-side buffer transistor is on; and coupling the drain conduction terminals of the buffer transistors of the low-side of the buffer to the high-side reference voltage when a high-side buffer transistor is on.

5 . The method of claim 3 wherein the buffer comprises:
a first half-bridge including:
a first high-side buffer transistor having a source terminal coupled to a first high-side voltage reference terminal;
a first high-side buffer diode coupled between a drain terminal of the first high-side buffer transistor and a central buffer node;
a first low-side buffer transistor having a source terminal coupled to a first low-side voltage reference terminal; and
a first low-side buffer diode coupled between a drain terminal of the first low-side buffer transistor and the central buffer node;

a second half-bridge including:
a second high-side buffer transistor having a source terminal coupled to a second high-side voltage reference terminal;
a second high-side buffer diode coupled between a drain terminal of the second high-side buffer transistor and the central buffer node;
a second low-side buffer transistor having a source terminal coupled to a second low-side voltage reference terminal; and
a second low-side buffer diode coupled between a drain terminal of the second low-side buffer transistor and the central buffer node; and

anti-memory circuitry configured to:
couple the drain terminal of the first high-side buffer transistor to at least one of the first low-side voltage reference terminal and the second low-side voltage reference terminal;
couple the drain terminal of the first low-side buffer transistor to at least one of the first high-side voltage reference terminal and the second high-side voltage reference terminal;
couple the drain terminal of the second high-side buffer transistor to at least one of the first low-side voltage reference terminal and the second low-side voltage reference terminal; and
couple the drain terminal of the second low-side buffer transistor to at least one of the first high-side voltage reference terminal and the second high-side voltage reference terminal.

6 . A system, comprising:
means for transmitting high-voltage pulses in a transmission phase; and means for coupling a high-side of the means for transmitting to a low-side reference voltage and coupling a low-side of the means for transmitting to a high-side reference voltage during a clamping phase.

7 . The system of claim 6 wherein the means for coupling is configured to:
couple drain conduction terminals of buffer transistors of the high-side of the means for transmitting to the low-side reference voltage during a receiving phase; and
couple drain conduction terminals of the buffer transistors of the low-side of the means for transmitting to the high-side reference voltage during the receiving phase.

8 . The system of claim 6 wherein the means for transmitting comprises:
a first half-bridge including:
a first buffer transistor having a first conduction terminal coupled to a first voltage reference terminal;
a first buffer diode coupled between a second conduction terminal of the first buffer transistor and a central buffer node;
a second buffer transistor having a first conduction terminal coupled to a second voltage reference terminal; and
a second buffer diode coupled between a second conduction terminal of the second buffer transistor and the central buffer node; and

a second half-bridge including:
a third buffer transistor having a first conduction terminal coupled to a third voltage reference terminal;
a third buffer diode coupled between a second conduction terminal of the third buffer transistor and the central buffer node;
a fourth buffer transistor having a first conduction terminal coupled to a fourth voltage reference terminal; and
a fourth buffer diode coupled between a second conduction terminal of the fourth buffer transistor and the central buffer node.

9 . The system of claim 8 wherein the means for coupling comprises:
a first switch coupled between the second conduction terminal of the first buffer transistor and the second voltage reference terminal;
a second switch coupled between the second conduction terminal of the third buffer transistor and the second voltage reference terminal;
a third switch coupled between the second conduction terminal of the second buffer transistor and the first voltage reference terminal; and
a fourth switch coupled between the second conduction terminal of the fourth buffer transistor and the first voltage reference terminal.

10 . The system of claim 9 wherein,
the first buffer transistor is a P-MOS transistor and the second conduction terminal of the first buffer transistor is a drain of the first buffer transistor;
the second buffer transistor is an N-MOS transistor and the second conduction terminal of the second buffer transistor is a drain of the second buffer transistor;
the third buffer transistor is a P-MOS transistor and the second conduction terminal of the third buffer transistor is a drain of the third buffer transistor; and
the fourth buffer transistor is an N-MOS transistor and the second conduction terminal of the fourth buffer transistor is a drain of the fourth buffer transistor.

11 . The system of claim 9 wherein the means for coupling comprises:
a controller, which, in operation, generates control signals to:
close the first, second, third and fourth switches during a clamping phase of operation; and
close the first, second, third and fourth switches during a receiving phase of operation.

12 . The system of claim 11 wherein the controller, in operation, generates control signals to:
close the first, second and fourth switches when the second buffer transistor is closed;
close the first, second and third switches when the fourth buffer transistor is closed;
close the second, third and fourth switches when the first buffer transistor is closed; and
close the first, third and fourth switches when the third buffer transistor is closed.

13 . The system of claim 8 wherein the means for coupling comprises:
a first switch having a first conduction terminal coupled to the second voltage reference termina

Assignees

• St Microelectronics Srl

Inventors

• Ghisu Davide Ugo
• Rossi Sandro
• Bianchi Dario

Classifications

• B06B1/0215 Primary

  for generating pulses, e.g. bursts of oscillations, envelopes · CPC title

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title

• H03K17/0822

  in field-effect transistor switches · CPC title

• H03K3/356182

  with additional means for controlling the main nodes · CPC title

• A61B8/4483

  characterised by features of the ultrasound transducer · CPC title