System and Method for Optimizing System Memory and Input/Output Operations Memory

Patent metadata

Field	Value
Publication number	US-2016328317-A1
Application number	US-201514707397-A
Country	US
Kind code	A1
Filing date	May 8, 2015
Priority date	May 8, 2015
Publication date	Nov 10, 2016
Grant date	—

Abstract

An information handling system including a first memory to store data as a system memory for operations of a first processor in the information handling system, a second memory to store data as a cache memory for input/output operations of a second processor, and an interrupt handler. The interrupt handler is configured to monitor an input/output bus to determine whether a number of the input/output operations is above a first threshold level, if the number of the input/output operations is above the threshold level, to re-allocate a portion of the first memory from the first processor to the second processor, to monitor the utilization of the first memory to determine whether a utilization level is above a second threshold level, and if the utilization level is above the second threshold level, to re-allocate a portion of the second memory from the second processor to the first processor.

First claim

What is claimed is:

1 . An information handling system comprising:
a first memory to store data as a system memory for operations of a first processor in the information handling system; a second memory to store data as a cache memory for input/output operations of a second processor in the information handling system; and an interrupt handler of a basic input/output system configured to communicate with the first and second processors, the interrupt handler to monitor an input/output bus of the information handling system to determine whether a number of the input/output operations is above a first threshold level, if the number of the input/output operations is above the first threshold level then to re-allocate a portion of the first memory from the first processor to the second processor, to monitor the utilization of the first memory to determine whether a utilization level is above a second threshold level, and if the utilization level is above the second threshold level then to re-allocate a portion of the second memory from the second processor to the first processor.

2 . The information handling system of claim 1 , wherein the second memory is located within a memory controller of the information handling system.

3 . The information handling system of claim 1 , the interrupt handler further to determine that the utilization level is above the second threshold as a result of a high data payload workload for the first processor, and to re-allocate the portion of the second memory as a block storage for the first processor separate from the first memory in response to the high data payload workload.

4 . The information handling system of claim 1 , the interrupt handler further to determine that the utilization level is above the second threshold as a result of a high frequency access workload for the first processor, and to re-allocate the portion of the second memory as a virtual memory extension of the first memory in response to the high frequency access workload.

5 . The information handling system of claim 1 , the interrupt handler further to periodically providing a system management interrupt, to send a command to the second processor in response to the system management interrupt, and to determine whether a storage amount of the second memory is being exceeded by an amount of data associated with the input/output operations for the second processor in response to the command.

6 . The information handling system of claim 1 , the interrupt handler further to periodically providing a system management interrupt, to determine a value of a machine specific register of the first processor of the information handling system in response to the system management interrupt, and to determine the utilization level of the first memory based on the value of the machine specific register.

7 . The information handling system of claim 1 , the interrupt handler further to determine a value of chipset specific registers, and to determine the utilization level of the first memory based on the value of the machine specific register.

8 . A method comprising:
utilizing a first memory of an information handling system as a system memory for operations of a first processor in the information handling system; utilizing a second memory of an information handling system as a cache memory for input/output operations of a second processor in the information handling system; monitoring an input/output bus of the information handling system to determine whether a number of the input/output operations is above a first threshold level; if the number of the input/output operations is above the threshold level, then re-allocating a portion of the first memory from the first processor to the second processor; monitoring the utilization of the first memory to determine whether a utilization level is above a second threshold level; and if the utilization level is above the second threshold level, then re-allocating a portion of the second memory from the second processor to the first processor.

9 . The method of claim 8 , wherein the second memory is located within a memory controller of the information handling system.

10 . The method of claim 8 , further comprising:
determining that the utilization level is above the second threshold as a result of a high data payload workload for the first processor; and re-allocating the portion of the second memory as a block storage for the first processor separate from the first memory in response to the high data payload workload.

11 . The method of claim 8 , wherein re-allocating the portion of the second memory from the second processor to the first processor comprises:
determining that the utilization level is above the second threshold as a result of a high frequency access workload for the first processor; and re-allocating the portion of the second memory as a virtual memory extension of the first memory in response to the high frequency access workload.

12 . The method of claim 8 , wherein monitoring the input/output bus of the information handling system comprises:
periodically providing a system management interrupt; sending a command to the second processor in response to the system management interrupt; and determining whether a storage amount of the second memory is being exceeded by an amount of data associated with the input/output operations for the second processor in response to the command.

13 . The method of claim 8 , wherein monitoring the utilization of the first memory comprises:
periodically providing a system management interrupt; determining, by a basic input/output system (BIOS) system management interrupt (SMI) handler, a value of a machine specific register of the first processor of the information handling system in response to the system management interrupt; and determining the utilization level of the first memory based on the value of the machine specific register.

14 . The method of claim 13 , wherein monitoring the utilization of the first memory comprises:
determining a value of chipset specific registers; and determining the utilization level of the first memory based on the value of the machine specific register.

15 . A method comprising:
utilizing a first memory of an information handling system as a system memory for operations of a first processor in the information handling system; utilizing a second memory of an information handling system as a cache memory for input/output operations of a second processor in the information handling system; monitoring the utilization of the first memory to determine whether a utilization level is above a second threshold level; and if the utilization level is above the second threshold level, then re-allocating a portion of the second memory from the second processor to the first processor.

16 . The method of claim 15 , wherein the second memory is located within a memory controller of the information handling system.

17 . The method of claim 15 , further comprising:
determining that the utilization level is above the second threshold as a result of a high data payload workload for the first processor; and re-allocating the portion of the second memory as a block storage for the first processor separate from the first memory in response to the high data payload workload.

18 . The method of claim 15 , wherein re-allocating the portion of the second memory from the second processor to the first processor comprises:
determining that the utilization level is above the second threshold as a result of

Assignees

• Dell Products Lp

Inventors

• Herzi Dirie N
• Farhan Munif

Classifications

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F12/023 Primary

  Free address space management · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title