Substrate structures and methods of manufacture

Patent metadata

Field	Value
Publication number	US-2016324008-A1
Application number	US-201615206574-A
Country	US
Kind code	A1
Filing date	Jul 11, 2016
Priority date	Nov 6, 2014
Publication date	Nov 3, 2016
Grant date	—

Abstract

A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.

First claim

What is claimed is:

1 . A method of forming an insulated metal substrate (IMS) for a power electronic, comprising:
partially etching a first surface of a copper layer to form a pattern comprising a first thickness and a second thickness greater than the first thickness, the first thickness and the second thickness both measured perpendicular to a second surface of the copper layer opposite the first surface of the copper layer; laminating the first surface of the copper layer with a second surface of a dielectric layer, the dielectric layer coupled to a metallic baseplate at a first surface of the dielectric layer opposite the second surface of the dielectric layer and at a second surface of the metallic baseplate; and forming traces in the copper layer by etching through the copper layer at the first thickness and etching through the copper layer at the second thickness, wherein the traces comprise two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the first surface of the dielectric layer.

2 . The method of claim 1 , wherein forming the pattern further comprises forming a third thickness different in magnitude from the first thickness and the second thickness, the third thickness measured perpendicular to the first surface of the dielectric layer.

3 . The method of claim 1 , further comprising plating a layer of nickel onto the second surface of the copper layer, and wherein forming the traces in the copper layer further comprises etching through the layer of nickel.

4 . The method of claim 1 , wherein etching through the copper layer at the first thickness and etching through the copper layer at the second thickness comprises coupling a first layer of photoresist to the second surface of the copper layer, forming a pattern in the first layer of photoresist, etching through the copper layer at the first thickness at spaces in the pattern in the first layer of photoresist, removing the first layer of photoresist, coupling a second layer of photoresist to the second surface of the copper layer, forming a pattern in the second layer of photoresist, etching through the copper layer at the second thickness at the spaces in the pattern in the second layer of photoresist, and removing the second layer of photoresist.

5 . The method of claim 1 , further comprising laminating the traces in the copper layer with a second dielectric layer, coupling a second copper layer to the second dielectric layer, and forming traces in the second copper layer to form a stacked IMS for a power electronic.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Lin Yusheng
• Takakusaki Sadamichi

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W70/6875

  being on a metallic substrate, e.g. insulated metal substrates [IMS] · CPC title

• H10W70/692

  Ceramics or glasses · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title