Integrated circuit comprising at least an integrated antenna

Patent metadata

Field	Value
Publication number	US-2016322269-A1
Application number	US-201615208269-A
Country	US
Kind code	A1
Filing date	Jul 12, 2016
Priority date	Jul 28, 2011
Publication date	Nov 3, 2016
Grant date	—

Abstract

An integrated circuit on a substrate includes a peripheral portion that surrounds an active area and is positioned close to a scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in the peripheral portion on different planes of metallizations starting from the substrate and forms an integrated antenna. Magnetic trench structures are provided adjacent the integrated antenna.

First claim

1 . An integrated circuit, comprising:
a substrate having a top surface; an insulating region above the top surface, said insulating region including metallizations; an antenna structure located in an area within scribe lines of the integrated circuit, said antenna structure formed by antenna lines arranged in different planes of said metallizations; a trench extending at least partially through a thickness of the substrate, said trench located adjacent the antenna structure; and a magnetic material located within said trench.

2 . The integrated circuit of claim 1 , further comprising a peripheral portion of the integrated circuit that surrounds an active circuit area, said peripheral portion located adjacent the scribe lines, wherein the antenna structure lies within the peripheral portion.

3 . The integrated circuit of claim 2 , wherein the trench is extends to a location between the antenna structure and the scribe line.

4 . The integrated circuit of claim 2 , wherein the trench is extends to a location between the antenna structure and the active circuit area.

5 . The integrated circuit of claim 1 , wherein said trench includes sidewalls and a bottom, and wherein said magnetic material lines said sidewalls and bottom of the trench.

6 . The integrated circuit of claim 5 , further including an insulating material filling a region between the magnetic material that lines said sidewalls.

7 . The integrated circuit of claim 1 , wherein said trench forms an isolation region within said substrate.

8 . An integrated circuit, comprising:
a substrate having a top surface; an insulating region above the top surface, said insulating region including metallizations; an antenna structure within a peripheral portion of the integrated circuit that surrounds an active circuit area, said peripheral portion located adjacent a scribe line, said antenna structure formed by antenna lines arranged in different planes of said metallizations; a first trench extending at least partially through a thickness of the insulating region, said first trench located within the peripheral portion adjacent the antenna structure; and a magnetic material located within said first trench.

9 . The integrated circuit of claim 8 , wherein the first trench is positioned between the antenna structure and the scribe line.

10 . The integrated circuit of claim 8 , wherein the first trench is positioned between the antenna structure and the active circuit area.

11 . The integrated circuit of claim 8 , wherein said first trench includes sidewalls and a bottom, and wherein said magnetic material lines said sidewalls and bottom of the first trench.

12 . The integrated circuit of claim 11 , further including an insulating material filling a region between the magnetic material that lines said sidewalls.

13 . The integrated circuit of claim 8 , wherein said first trench extends completely through the thickness of the insulating region.

14 . The integrated circuit of claim 8 , wherein said first trench extends completely through the thickness of the insulating region and penetrates at least partially through the substrate.

15 . The integrated circuit of claim 14 , further including an isolation region within said substrate, wherein the first trench penetrates into the isolation region.

16 . The integrated circuit of claim 8 , further including an isolation region within said substrate, wherein said antenna structure and first trench are located above the isolation region.

17 . The integrated circuit of claim 16 , wherein said first trench extends along a sidewall of the isolation region.

18 . The integrated circuit of claim 16 , further including a further magnetic material extending along a bottom of the isolation region and in contact with the magnetic material within the first trench.

19 . The integrated circuit of claim 16 , wherein the isolation region is a through silicon via structure within the substrate and filled with an insulating material.

20 . The integrated circuit of claim 16 , further comprising:
a second trench extending at least partially through a thickness of the isolation region; and a further magnetic material located within said second trench.

21 . The integrated circuit of claim 20 , wherein said second trench includes sidewalls and a bottom, and wherein said further magnetic material lines said sidewalls and bottom of the second trench.

22 . The integrated circuit of claim 21 , further including an insulating material filling a region between the magnetic material that lines said sidewalls.

23 . The integrated circuit of claim 20 , wherein said first and second trenches are vertically aligned with each other.

24 . An integrated circuit, comprising:
a substrate having a top surface; an insulating region above the top surface, said insulating region including metallizations; an antenna structure within a peripheral portion of the integrated circuit that surrounds an active circuit area, said peripheral portion located adjacent a scribe line, said antenna structure formed by antenna lines arranged in different planes of said metallizations; a first trench extending at least partially through a thickness of the insulating region, said first trench located within the peripheral portion between the antenna structure and the scribe line; a second trench extending at least partially through the thickness of the insulating region, said second trench located within the peripheral portion between the antenna structure and the active circuit area; and a magnetic material located within said first and second trenches.

25 . The integrated circuit of claim 24 , wherein said first and second trenches include sidewalls and a bottom, and wherein said magnetic material lines said sidewalls and bottom of the first and second trenches.

26 . The integrated circuit of claim 25 , further including an insulating material filling a region between the magnetic material that lines said sidewalls.

27 . The integrated circuit of claim 24 , wherein said first and second trenches extend completely through the thickness of the insulating region and penetrate at least partially through the substrate.

28 . The integrated circuit of claim 27 , further including an isolation region within said substrate, wherein the first and second trenches penetrate into the isolation region.

29 . The integrated circuit of claim 28 , further including a further magnetic material extending along a bottom of the isolation region and in contact with the magnetic material within the first and second trenches.

30 . The integrated circuit of claim 24 , further including an isolation region within said substrate, wherein said antenna structure and first and second trenches are located above the isolation region.

31 . The integrated circuit of claim 30 , further including:
a third trench extending at least partially through a thickness of the isolation region, said third trench positioned in vertical alignment with the first trench between the antenna structure and the scribe line; a fourth trench extending at least partially through the thickness of the isolation region, said fourth trench positioned in vertical alignment with the second trench between the antenna structure and the active circuit area; and a furt

Assignees

• St Microelectronics Srl

Inventors

• Pagani Alberto
• Finocchiaro Alessandro

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title