Method and apparatus for detection of failures in under-fill layers in integrated circuit assemblies

Patent metadata

Field	Value
Publication number	US-2016322265-A1
Application number	US-201514700639-A
Country	US
Kind code	A1
Filing date	Apr 30, 2015
Priority date	Apr 30, 2015
Publication date	Nov 3, 2016
Grant date	—

Abstract

A methodology and circuitry enabling detection of smaller and early stages of failures in under-fill layers in IC chip assemblies are disclosed. Embodiments include providing a top plate having an upper surface and a lower surface, the lower surface bonded by a bonding material layer to an upper surface of a bottom plate; forming transmitter and receiver asymmetric coupling capacitors between the top plate and the bottom plate; forming a transmission line in the bottom plate connecting elements of the transmitter and receiver asymmetric coupling capacitors in the bottom plate; and detecting a failure in the bonding material layer based, at least in part, on electrical characteristics associated with the transmitter asymmetric coupling capacitor, the receiver asymmetric coupling capacitor, the transmission line or a combination thereof.

First claim

What is claimed is:

1 . A method comprising:
providing a top plate having an upper surface and a lower surface, the lower surface bonded by a bonding material layer to an upper surface of a bottom plate; forming transmitter and receiver asymmetric coupling capacitors between the top plate and the bottom plate; forming a transmission line in the bottom plate connecting elements of the transmitter and receiver asymmetric coupling capacitors in the bottom plate; and detecting a failure in the bonding material layer based, at least in part, on electrical characteristics associated with the transmitter asymmetric coupling capacitor, the receiver asymmetric coupling capacitor, the transmission line or a combination thereof.

2 . The method according to claim 1 , further comprising:
determining the electrical characteristics based, at least in part, on variations in a capacitance, a leakage current, or a combination thereof associated with the transmitter or receiver asymmetric coupling capacitors.

3 . The method according to claim 1 , further comprising:
determining the electrical characteristics based, at least in part, on variations in a data transfer through the transmission line.

4 . The method according to claim 1 , wherein forming the transmitter asymmetric coupling capacitor comprises:
forming a top transmitter element at the lower surface of the top plate and a bottom transmitter element at the upper surface of the bottom plate.

5 . The method according to claim 4 , wherein forming the receiver asymmetric coupling capacitor comprises:
forming a top receiver element at the lower surface of the top plate and a bottom receiver element at the upper surface of the bottom plate.

6 . The method according to claim 5 , further comprising:
forming the top transmitter and receiver elements in a metal layer of the top layer; and forming the bottom transmitter and receiver elements in a metal layer of the bottom plate.

7 . The method according to claim 1 , further comprising:
forming a test system interface in the top plate including test pads electrically coupled to each element of the transmitter and receiver asymmetric coupling capacitors in the top plate.

8 . The method according to claim 1 , wherein the top plate is a silicon layer.

9 . The method according to claim 1 , wherein the bottom plate is a substrate layer or another silicon layer.

10 . The method according to claim 1 , wherein the failure in the bonding material layer includes a delamination, a void, a crack or a combination thereof.

11 . A semiconductor device comprising:
a top plate having an upper surface and a lower surface, the lower surface bonded by a bonding material layer to an upper surface of a bottom plate; transmitter and receiver asymmetric coupling capacitors between the top plate and the bottom plate; a transmission line in the bottom plate connecting elements of the transmitter and receiver asymmetric coupling capacitors in the bottom plate; and a test system interface in the top plate including test pads electrically coupled to each element of the transmitter and receiver asymmetric coupling capacitors in the top plate.

12 . The semiconductor device according to claim 11 , wherein the transmitter asymmetric coupling capacitor comprises:
a top transmitter element at the lower surface of the top plate and a bottom transmitter element at the upper surface of the bottom plate.

13 . The semiconductor device according to claim 12 , wherein the receiver asymmetric coupling capacitor comprises:
a top receiver element at the lower surface of the top plate and a bottom receiver element at the upper surface of the bottom plate.

14 . The semiconductor device according to claim 13 , wherein the top transmitter and receiver elements are formed in a metal layer of the top layer, and the bottom transmitter and receiver elements are formed in a metal layer of the bottom plate.

15 . The semiconductor device according to claim 11 , wherein the top plate is a silicon layer.

16 . The semiconductor device according to claim 11 , wherein the bottom plate is a substrate layer or another silicon layer.

17 . A method comprising:
providing a top plate having an upper surface and a lower surface, the lower surface bonded by a bonding material layer to an upper surface of a bottom plate, wherein the top plate is a silicon layer and the bottom plate is a substrate layer or another silicon layer; forming transmitter and receiver asymmetric coupling capacitors between the top plate and the bottom plate; forming a transmission line in the bottom plate connecting elements of the transmitter and receiver asymmetric coupling capacitors in the bottom plate; determining electrical characteristics based, at least in part, on variations in a capacitance, a leakage current, or a combination thereof associated with the transmitter or receiver asymmetric coupling capacitors; and detecting a failure in the bonding material layer based, at least in part, on the electrical characteristics.

18 . The method according to claim 1 , further comprising:
determining the electrical characteristics based, at least in part, on variations in a data transfer through the transmission line.

19 . The method according to claim 1 , further comprising:
forming a top transmitter element in a metal layer at the lower surface of the top plate and a bottom transmitter element in a metal layer at the upper surface of the bottom plate; and forming a top receiver element in the metal layer at the lower surface of the top plate and a bottom receiver element in the metal layer at the upper surface of the bottom plate.

20 . The method according to claim 1 , further comprising:
forming a test system interface in the top plate including test pads electrically coupled to each element of the transmitter and receiver asymmetric coupling capacitors in the top plate.

Assignees

• Globalfoundries Inc

Inventors

• Gao Shan
• Kannan Sukeshwar

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W74/012

  of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills · CPC title

• H10P72/0604

  Process monitoring, e.g. flow or thickness monitoring · CPC title