Low Defect Relaxed SiGe/Strained Si Structures on Implant Anneal Buffer/Strain Relaxed Buffer Layers with Epitaxial Rare Earth Oxide Interlayers and Methods to Fabricate Same

Patent metadata

Field	Value
Publication number	US-2016322221-A1
Application number	US-201615047838-A
Country	US
Kind code	A1
Filing date	Feb 19, 2016
Priority date	Apr 30, 2015
Publication date	Nov 3, 2016
Grant date	—

Abstract

A method provides a substrate having a top surface; forming a first semiconductor layer on the top surface, the first semiconductor layer having a first unit cell geometry; epitaxially depositing a layer of a metal-containing oxide on the first semiconductor layer, the layer of metal-containing oxide having a second unit cell geometry that differs from the first unit cell geometry; ion implanting the first semiconductor layer through the layer of metal-containing oxide; annealing the ion implanted first semiconductor layer; and forming a second semiconductor layer on the layer of metal-containing oxide, the second semiconductor layer having the first unit cell geometry. The layer of metal-containing oxide functions to inhibit propagation of misfit dislocations from the first semiconductor layer into the second semiconductor layer. A structure formed by the method is also disclosed.

First claim

What is claimed is:

1 . A method comprising:
providing a substrate having a top surface; forming a first semiconductor layer on the top surface of the substrate, the first semiconductor layer having a first unit cell geometry; epitaxially depositing a layer comprised of a metal-containing oxide on the first semiconductor layer, the layer of metal-containing oxide having a second unit cell geometry that differs from the first unit cell geometry; ion implanting the first semiconductor layer through the layer comprised of a metal-containing oxide; annealing the ion implanted first semiconductor layer; and forming a second semiconductor layer on the layer comprised of a metal-containing oxide, the second semiconductor layer having the first unit cell geometry.

2 . The method of claim 1 , wherein the first semiconductor material and the second semiconductor material are both comprised of Si 1−x Ge x , and where the metal-containing oxide layer is comprised of a rare earth metal.

3 . The method of claim 1 , wherein the first semiconductor material and the second semiconductor material are both comprised of Si 1−x Ge x , and where the metal-containing oxide layer is comprised of at least one of cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), yttrium oxide (Y 2 O 3 ), gadolinium oxide (Gd 2 O 3 ), europium oxide (Eu 2 O 3 ), terbium oxide (Tb 2 O 3 ), a material ABO 3 , where ‘A’ and ‘B’ may be any rare earth metal including lanthanum scandium oxide (LaScO 3 ) and lanthanum yttrium oxide (La x Y 1−x ) 2 O 3 , samarium yttrium oxide (Sm x Y 1−x ) 2 O 3 ), lanthanum gadolinium oxide (La x Gd 1−x ) 2 O 3 ), and gadolinium europium oxide (Gd x Eu 1−x ) 2 O 3 ).

4 . The method of claim 1 , where the step of implanting forms dislocation nucleation centers in the first semiconductor layer, where the step annealing forms misfit dislocations originating from the nucleation centers, and where the metal-containing oxide layer inhibits propagation of the misfit dislocations into the second semiconductor layer.

5 . The method of claim 1 , where the first semiconductor layer is formed as a strained layer comprised of Si 1−x Ge x , and where the step of annealing strain relaxes the first semiconductor layer.

6 . The method of claim 1 , where the first unit cell geometry exhibits a diamond lattice crystal structure, and where the second unit cell geometry exhibits is a cubic lattice crystal structure.

7 . The method of claim 1 , where the step of epitaxially depositing the layer comprised of the metal-containing oxide deposits the layer to have a thickness in a range of about 10 nm to about 100 nm, or a thickness in an range of about 20 nm to about 50 nm, or to have a thickness of about 30 nm.

8 . The method as in claim 1 , where the second semiconductor layer is Si 1−x Ge x , and further comprising depositing a layer of strained silicon on a top surface of the second semiconductor layer.

9 . The method as in claim 1 , where the first semiconductor layer is Si 1−x Ge x , and further comprising depositing a further layer of Si 1−x Ge x on a top surface of the second semiconductor layer, where the value of x in the further layer of Si 1−x Ge x concentration is greater than the value of x in the first semiconductor layer.

10 . A structure, comprising:
a substrate having a top surface; a first semiconductor layer disposed on the top surface of the substrate, the first semiconductor layer having a first unit cell geometry; a layer comprised of a metal-containing oxide disposed on the first semiconductor layer, the layer of metal-containing oxide having a second unit cell geometry that differs from the first unit cell geometry to inhibit propagation of misfit dislocations from the first semiconductor layer into the second semiconductor layer; and a second semiconductor layer disposed on the layer comprised of the metal-containing oxide, the second semiconductor layer having the first unit cell geometry.

11 . The structure of claim 10 , wherein the first semiconductor material and the second semiconductor material are both comprised of Si 1−x Ge x , and where the metal-containing oxide layer is comprised of a rare earth metal.

12 . The structure of claim 10 , wherein the first semiconductor material and the second semiconductor material are both comprised of Si x Ge x , and where the metal-containing oxide layer is comprised of at least one of cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), yttrium oxide (Y 2 O 3 ), gadolinium oxide (Gd 2 O 3 ), europium oxide (Eu 2 O 3 ), terbium oxide (Tb 2 O 3 ), a material ABO 3 , where ‘A’ and ‘B’ may be any rare earth metal including lanthanum scandium oxide (LaScO 3 ) and lanthanum yttrium oxide (La x Y 1−x ) 2 O 3 , samarium yttrium oxide (Sm x Y 1−x ) 2 O 3 ), lanthanum gadolinium oxide (La x Gd 1−x ) 2 O 3 ), and gadolinium europium oxide (Gd x Eu 1−x ) 2 O 3 ).

13 . The structure of claim 10 , where the misfit dislocations originate from nucleation centers formed by implanted ions.

14 . The structure of claim 10 , where the first semiconductor layer is a strain relaxed layer comprised of Si 1−x Ge x .

15 . The structure of claim 10 , where the first unit cell geometry exhibits a diamond lattice crystal structure, and where the second unit cell geometry exhibits is a cubic lattice crystal structure.

16 . The structure of claim 10 , where the layer comprised of the metal-containing oxide has a thickness in a range of about 10 nm to about 100 nm, or a thickness in a range of about 20 nm to about 50 nm, or a thickness of about 30 nm.

17 . The structure of claim 10 , where the second semiconductor layer is Si 1−x Ge x , and further comprising a layer of strained silicon on a top surface of the second semiconductor layer.

18 . The structure of claim 10 , where the first semiconductor layer is Si 1−x Ge x , and further comprising a further layer of Si 1−x Ge x on a top surface of the second semiconductor layer, where the value of x in the further layer of Si 1−x Ge x concentration is greater than the value of x in the first semiconductor layer.

19 . The structure of claim 10 , embodied as an intermediate structure during fabrication of an integrated circuit.

Assignees

• IBM

Inventors

• Reznicek Alexander

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P14/69397

  the material containing two or more metal elements · CPC title

• H10P14/69396

  the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title