Display source driver

US2016321977A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016321977-A1
Application numberUS-201615006618-A
CountryUS
Kind codeA1
Filing dateJan 26, 2016
Priority dateApr 30, 2015
Publication dateNov 3, 2016
Grant date

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Abstract

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A source driver for a display device includes a gamma voltage generation circuit, first through (2m)-th data driving circuits, and a switch circuit. The gamma voltage generation circuit generates R, G and B gamma voltages. The (2k−1)-th data driving circuits consecutively receive red image data and blue image data, and consecutively generate a R driving voltage and a B driving voltage using the R gamma voltages and B gamma voltages, respectively, during one horizontal period. The (2k)-th data driving circuits consecutively receive first green image data and second green image data, and consecutively generate a G1 driving voltage and a G2 driving voltage, respectively, using the G gamma voltages during the one horizontal period. The switch circuit outputs the R, B, G1, and G2 driving voltages through different data lines from each other based on a first selection signal and a second selection signal.

First claim

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What is claimed is: 1 . A source driver for a display device, comprising: a gamma voltage generation circuit configured to generate R gamma voltages, G gamma voltages, and B gamma voltages; (2k−1)-th data driving circuits configured to consecutively receive both red image data and blue image data during one horizontal period, and to consecutively generate both a R driving voltage and a B driving voltage, which correspond to the red image data and the blue image data, using the R gamma voltages and B gamma voltages, respectively, during the one horizontal period, k being all positive integers equal to or smaller than m, m being a positive integer; (2k)-th data driving circuits configured to consecutively receive both first green image data and second green image data during the one horizontal period, and to consecutively generate both a G1 driving voltage and a G2 driving voltage, which correspond to the first green image data and the second green image data, respectively, using the G gamma voltages during the one horizontal period; and a switch circuit configured to output the R driving voltage, the B driving voltage, the G1 driving voltage, and the G2 driving voltage, which are received from the first through (2m)-th data driving circuits during the one horizontal period, through different data lines from each other based on a first selection signal and a second selection signal. 2 . The source driver of claim 1 , wherein the first selection signal and the second selection signal are activated alternately during the one horizontal period. 3 . The source driver of claim 1 , wherein the switch circuit outputs the R driving voltage and the B driving voltage, which are received from the (2i−1)-th data driving circuit during the one horizontal period, through a (4i−3)-th data line and a (4i−1)-th data line, respectively, based on the first selection signal and the second selection signal, and outputs the G1 driving voltage and the G2 driving voltage, which are received from the (2i)-th data driving circuit during the one horizontal period, through a (4i−2)-th data line and a (4i)-th data line, respectively, based on the first selection signal and the second selection signal, where i is a positive integer equal to or smaller than m. 4 . The source driver of claim 1 , wherein the switch circuit includes first through (2m)-th demultiplexers coupled to the first through (2m)-th data driving circuits, respectively, and each of the first through (2m)-th demultiplexers consecutively outputs two driving voltages, which are received from a corresponding data driving circuit during the one horizontal period, through different data lines from each other based on the first selection signal and the second selection signal. 5 . The source driver of claim 4 , wherein the (2i−1)-th demultiplexer includes: a first switch coupled between the (2i−1)-th data driving circuit and a (4i−3)-th data line, the first switch being configured to turn on in response to the first selection signal; and a second switch coupled between the (2i−1)-th data driving circuit and a (4i−1)-th data line, the second switch being configured to turn on in response to the second selection signal, and wherein the (2i)-th demultiplexer includes: a third switch coupled between the (2i)-th data driving circuit and a (4i−2)-th data line, the third switch being configured to turn on in response to the first selection signal; and a fourth switch coupled between the (2i)-th data driving circuit and a (4i)-th data line, the fourth switch being configured to turn on in response to the second selection signal, where i is a positive integer equal to or smaller than m. 6 . The source driver of claim 1 , wherein the order in which each of the (2k−1)-th data driving circuits receives the red image data and the blue image data during an odd horizontal period is opposite to the order in which each of the (2k−1)-th data driving circuits receives the red image data and the blue image data during an even horizontal period, and wherein the order in which the first selection signal and the second selection signal are alternately activated during the odd horizontal period is the same as the order in which the first selection signal and the second selection signal are alternately activated during the even horizontal period. 7 . The source driver of claim 1 , wherein the order in which each of the (2k−1)-th data driving circuits receives the red image data and the blue image data during an odd horizontal period is the same as the order in which each of the (2k−1)-th data driving circuits receives the red image data and the blue image data during an even horizontal period, and wherein the order in which the first selection signal and the second selection signal are alternately activated during the odd horizontal period is opposite to the order in which the first selection signal and the second selection signal are alternately activated during the even horizontal period. 8 . The source driver of claim 1 , wherein the gamma voltage generation circuit includes: a first gamma voltage generator configured to generate the R gamma voltages and the B gamma voltages alternately during the one horizontal period based on a logic level of a gamma selection signal, and to provide the R gamma voltages and the B gamma voltages to the (2k−1)-th data driving circuits; and a second gamma voltage generator configured to generate the G gamma voltages, and to provide the G gamma voltages to the (2k)-th data driving circuits. 9 . The source driver of claim 1 , wherein the gamma voltage generation circuit includes: a first gamma voltage generator configured to generate the R gamma voltages; a second gamma voltage generator configured to generate the B gamma voltages; a third gamma voltage generator configured to generate the G gamma voltages, and to provide the G gamma voltages to the (2k)-th data driving circuits; and a multiplexer configured to provide one of the R gamma voltages and the B gamma voltages to the (2k−1)-th data driving circuits based on a logic level of a gamma selection signal. 10 . The source driver of claim 9 , wherein the gamma selection signal has a first logic level during a first half of the one horizontal period, and has a second logic level during a second half of the one horizontal period. 11 . The source driver of claim 1 , further comprising: a data latch circuit configured to receive the red image data, the first green image data, the second green image data, and the blue image data, to consecutively provide the red image data and the blue image data to the (2k−1)-th data driving circuits during the one horizontal period, and to consecutively provide the first green image data and the second green image data to the (2k)-th data driving circuits during the one horizontal period. 12 . A display device, comprising: a display panel including red subpixels, green subpixels, and blue subpixels coupled to a plurality of gate lines and a plurality of data lines; a gate driver configured to consecutively select the plurality of gate lines; a source driver configured to provide a plurality of driving voltages to the plurality of data lines; and a controller configured to control the gate driver and the source driver, and to provide image data to the source driver, wherein the source driver includes data driving circuits, the number of which is half of the number of the plurality of data lines, first half of the data driving circuits generate both a R driving voltage and a B driving voltage, which correspond to red image data and blue image data, respectively, that are consecutively received during one ho

Assignees

Inventors

Classifications

  • Generation of voltages supplied to electrode drivers in a matrix display other than LCD · CPC title

  • G09G3/2003Primary

    Display of colours (specific for liquid crystal displays G09G3/3607) · CPC title

  • Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

  • for control of gamma adjustment, e.g. selecting another gamma curve · CPC title

  • Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

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What does patent US2016321977A1 cover?
A source driver for a display device includes a gamma voltage generation circuit, first through (2m)-th data driving circuits, and a switch circuit. The gamma voltage generation circuit generates R, G and B gamma voltages. The (2k−1)-th data driving circuits consecutively receive red image data and blue image data, and consecutively generate a R driving voltage and a B driving voltage using the…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/2003. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Nov 03 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).