System and method for creating aliased mappings to minimize impact of cache invalidation

Patent metadata

Field	Value
Publication number	US-2016321773-A1
Application number	US-201514698024-A
Country	US
Kind code	A1
Filing date	Apr 28, 2015
Priority date	Apr 28, 2015
Publication date	Nov 3, 2016
Grant date	—

Abstract

A parallel processor and a method of reducing texture cache invalidation are disclosed. In one embodiment, the parallel processor includes a cache configured to receive lines of data; and a parallel execution unit associated with the cache and configured to execute parallel counterparts of an operation. The parallel counterparts, when executed, are configured to create, in the cache, corresponding aliases of a line of data pertaining to the operation such that the parallel counterparts are operable to invalidate only the corresponding aliases.

First claim

1 . A parallel processor, comprising:
a cache configured to receive lines of data; and a parallel execution unit associated with said cache and configured to execute parallel counterparts of an operation, said parallel counterparts, when executed, configured to create, in said cache, corresponding aliases of a line of data pertaining to said operation such that said parallel counterparts are operable to invalidate only said corresponding aliases.

2 . The parallel processor as recited in claim 1 wherein said aliases are created in said cache by executing a texture load.

3 . The parallel processor as recited in claim 1 wherein said parallel processor is a graphics processing unit.

4 . The parallel processor as recited in claim 1 wherein said operation includes blending color values to accomplish transparency.

5 . The parallel processor as recited in claim 1 wherein said parallel counterparts are configured to store said aliases by executing a surface store.

6 . The parallel processor as recited in claim 1 wherein said aliases include a copy of said line of data.

7 . The parallel processor as recited in claim 1 wherein said aliases correspond to said parallel counterparts based on a number of said parallel counterparts using said aliases.

8 . A method of reducing an impact of cache invalidation, comprising:
executing parallel counterparts of a surface operation that is to operate on a line of data; causing, with said parallel counterparts, corresponding aliases of said line of data to be loaded into a cache; and allowing said parallel counterparts of said operation to invalidate only said corresponding aliases.

9 . The method as recited in claim 8 wherein said cache is associated with a parallel processor and said aliases are loaded by executing a texture load.

10 . The method as recited in claim 8 wherein said parallel processor is a graphics processing unit.

11 . The method as recited in claim 8 wherein said cache is a texture cache.

12 . The method as recited in claim 11 wherein said aliases are stored by executing a surface store.

13 . The method as recited in claim 8 wherein said aliases include a copy of said line of data.

14 . The method as recited in claim 8 wherein said aliases correspond to said parallel counterparts based on a number of said parallel counterparts using said aliases.

15 . A surface operation in a library of graphics operations, said surface operation comprising:
executing parallel counterparts of said surface operation that is to operate on a line of data; causing, with said parallel counterparts, corresponding aliases of said line of data to be loaded into a cache; and allowing said parallel counterparts of said operation to invalidate only said corresponding aliases.

16 . The surface operation as recited in claim 15 wherein said aliases are loaded by executing a texture load.

17 . The surface operation as recited in claim 15 wherein said cache is a texture cache.

18 . The surface operation as recited in claim 15 wherein said aliases are stored by executing a surface store.

19 . The surface operation as recited in claim 15 wherein said aliases include a copy of said line of data.

20 . The surface operation as recited in claim 15 wherein said aliases correspond to said parallel counterparts based on a number of said parallel counterparts using said aliases.

Assignees

• Nvidia Corp

Inventors

• Bolz Jeffrey

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F12/0833

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06T1/60

  Memory management · CPC title

• G09G5/395

  Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen (G09G5/399 takes precedence) · CPC title