Semiconductor electroplating system

Patent metadata

Field	Value
Publication number	US-2016315048-A1
Application number	US-201615138167-A
Country	US
Kind code	A1
Filing date	Apr 25, 2016
Priority date	Apr 27, 2015
Publication date	Oct 27, 2016
Grant date	—

Abstract

A semiconductor electroplating system includes a conducting ring and at least one conductive device. The conducting ring is used for carrying a wafer. The conducting ring has at least two connecting points. The wafer has a first surface and an opposite second surface. An isolation layer is located on the second surface. Two ends of the conductive device are respectively connected to the two connecting points of the conducting ring. When the conducting ring is immersed in the plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer. The conductive device is used for transmitting a partial current that passes through one of the connecting points to the other connecting point.

First claim

What is claimed is:

1 . A semiconductor electroplating system, comprising:
a conducting ring for carrying a wafer, and having at least two connecting points, wherein the wafer has a first surface and an opposite second surface, and an isolation layer is located on the second surface; and at least one conductive device having two ends that are respectively connected to the connecting points of the conducting ring, wherein when the conducting ring is immersed in a plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer, wherein the conductive device is used for transmitting a partial current passing through one of the connecting points to the other connecting point.

2 . The semiconductor electroplating system of claim 1 , wherein the conducting ring has a top surface, a sidewall, and a supporting surface which are sequentially connected, and the sidewall surrounds an accommodating space, and the supporting surface protrudes from the accommodating space, such that the top surface, the sidewall and the supporting surface form a ladder structure.

3 . The semiconductor electroplating system of claim 2 , wherein the wafer is located on the supporting surface, and is surrounded by the sidewall.

4 . The semiconductor electroplating system of claim 2 , wherein the first surface of the wafer faces the supporting surface.

5 . The semiconductor electroplating system of claim 2 , wherein the connecting points and the conductive device are located on the top surface of the conducting ring.

6 . The semiconductor electroplating system of claim 1 , wherein the conductive device is an electric wire.

7 . A semiconductor electroplating system, comprising:
a conducting ring for carrying a wafer, and having a ring-shaped track, wherein the wafer has a first surface and an opposite second surface, and an isolation layer is located on the second surface; and at least one conductive piece having two ends, wherein each of the ends has a connecting point which is movably connected to the ring-shaped track of the conducting ring, and the conductive piece overlaps a portion of the conducting ring; when the conducting ring is immersed in a plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer, wherein the conductive piece is used for transmitting a partial current passing through one of the connecting points to the other connecting point.

8 . The semiconductor electroplating system of claim 7 , wherein the conducting ring has a top surface, a sidewall, and a supporting surface which are sequentially connected, and the sidewall surrounds an accommodating space, and the supporting surface protrudes from the accommodating space, such that the top surface, the sidewall and the supporting surface form a ladder structure.

9 . The semiconductor electroplating system of claim 8 , wherein the wafer is located on the supporting surface, and is surrounded by the sidewall.

10 . The semiconductor electroplating system of claim 8 , wherein the first surface of the wafer faces the supporting surface.

11 . The semiconductor electroplating system of claim 8 , wherein the ring-shaped track is located on the top surface of the conducting ring, and the two ends of the conductive piece are movably disposed on the ring-shaped track.

Assignees

• Xintec Inc

Inventors

• Ho Yen-Shih
• Chang Shu-Ming
• Shen Hsing-Lung
• Su Yu-Hao
• Wu Kuan-Jung
• Cheng Yi

Classifications

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10P72/7606

  characterised by edge clamping, e.g. clamping ring · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title