Digital predistortion for dual-band power amplifiers

Patent metadata

Field	Value
Publication number	US-2016308577-A1
Application number	US-201615191583-A
Country	US
Kind code	A1
Filing date	Jun 24, 2016
Priority date	Apr 17, 2013
Publication date	Oct 20, 2016
Grant date	—

Abstract

A signal processing circuit arrangement may include a preamplifier circuit configured to map a first dimension input and a second dimension input to a first subset of a plurality of lookup table coefficients of a two-dimensional (2D) lookup table, wherein the first dimension input and the second dimension input each represent a signal level of one or more input signals, extrapolate from the first subset of the plurality of lookup table coefficients to generate a lookup table output, and apply the lookup table output to the one or more input signals to generate a predistorted input signal for an amplifier.

First claim

What is claimed is:

1 . A signal processing circuit arrangement comprising:
a preamplifier circuit configured to: map a first dimension input and a second dimension input to a first subset of a plurality of lookup table coefficients of a two-dimensional (2D) lookup table, wherein the first dimension input and the second dimension input each represent a signal level of one or more input signals; extrapolate from the first subset of the plurality of lookup table coefficients to generate a lookup table output; and apply the lookup table output to the one or more input signals to generate a predistorted input signal for an amplifier.

2 . The signal processing circuit arrangement of claim 1 , further comprising the amplifier.

3 . The signal processing circuit arrangement of claim 2 , further comprising a mixing circuit configured to modulate the predistorted input signal with a radio frequency signal to obtain a modulated predistorted input signal,
wherein the amplifier configured is configured to amplify the predistorted input signal.

4 . The signal processing circuit arrangement of claim 1 , wherein the first dimension input represents a real part of a first complex sample of a first input signal of the one or more input signals and the second dimension input represents an imaginary part of the first complex sample of the first input signal.

5 . The signal processing circuit arrangement of claim 1 , wherein the first dimension input represents a signal level of a first input signal of the one or more input signals and the second dimension input represents a signal level of a second input signal of the one or more input signals.

6 . The signal processing circuit arrangement of claim 1 , wherein the preamplifier circuit is further configured to generate one or more additional lookup table outputs from one or more additional 2D lookup tables.

7 . The signal processing circuit arrangement of claim 6 , wherein the preamplifier circuit is configured to apply the lookup table output to the one or more input signals to generate the predistorted input signal for the amplifier by:
identifying one or more input samples of the one or more input signals; evaluating one or more functions of the one or more input samples to obtain one or more function outputs; and determining one or more intermediate products by multiplying each of the one or more function outputs by a respective lookup table output of the one or more additional lookup table outputs; and generating the predistorted input signal for the amplifier as a sum of the one or more intermediate products.

8 . The signal processing circuit arrangement of claim 7 , wherein each of the one or more input samples are samples of a first input signal of the one or more input signals.

9 . The signal processing circuit arrangement of claim 7 , wherein the one or more input samples comprise input samples of a first input signal of the one or more input signals and a second input signal of the one or more input signals.

10 . The signal processing circuit arrangement of claim 9 , wherein the amplifier is a dual-band amplifier, and wherein the first input signal corresponds to a first band of the dual-band amplifier and the second input signal corresponds to a second band of the dual-band amplifier.

11 . The signal processing circuit arrangement of claim 1 , wherein the preamplifier circuit is further configured to:
map the first dimension input and the second dimension input to one or more additional 2D lookup tables; interpolate or extrapolate with the one or more additional 2D lookup tables to generate one or more additional lookup table outputs, wherein the preamplifier circuit is configured to apply the lookup table output to the one or more input signals to generate the predistorted input signal for the amplifier by: combining the lookup table output and the one or more additional lookup table outputs to generate the predistorted input signal.

12 . The signal processing circuit arrangement of claim 1 , further comprising:
a feedback circuit configured to monitor an output signal of the amplifier; and an adaptation circuit configured to adapt the plurality of lookup table coefficients based on the output signal of the amplifier.

13 . The signal processing circuit arrangement of claim 12 , wherein the preamplifier circuit is further configured to:
assign each of a plurality of predefined regions of the 2D lookup table as an interpolation region or an extrapolation region; and reassign at least one of the plurality of predefined regions of the 2D lookup table.

14 . The signal processing circuit arrangement of claim 13 , wherein a point formed by the first dimension input and the second dimension input falls within an extrapolation region.

15 . The signal processing circuit arrangement of claim 13 , wherein the preamplifier circuit is configured to reassign the at least one of the plurality of predefined regions of the 2D lookup table by:
monitoring a plurality of pairs of first dimension inputs and second dimension inputs received for the 2D lookup table; and reassigning a first region of the plurality of predefined regions as an interpolation region if more than a predefined quantity of the plurality of pairs fall within the first region and reassigning the first region as an extrapolation region if less than the predefined quantity of the plurality of pairs fall within the first region.

16 . A signal processing circuit arrangement comprising:
a first DPD circuit configured to: to map a first dimension input and a second dimension input to one or more first two-dimensional (2D) lookup tables, wherein the first dimension input represents a signal level of a first input signal and the second dimension input represents a signal level of a second input signal, and to extrapolate from lookup table coefficients of a first 2D lookup table of the one or more first 2D lookup tables to obtain a first intermediate signal; a second DPD circuit configured to: map the first dimension input and the second dimension input to one or more second 2D lookup tables, and to interpolate or extrapolate with lookup table coefficients of the one or more second 2D lookup tables to obtain a second intermediate signal; and a combination circuit configured to combine the first intermediate signal and the second intermediate signal to obtain a predistorted input signal for an amplifier.

17 . The signal processing circuit arrangement of claim 16 , further comprising the amplifier.

18 . The signal processing circuit arrangement of claim 16 , wherein the combination circuit is configured to combine the first intermediate signal and the second intermediate signal to obtain the predistorted input signal by:
upsampling and upconverting the first intermediate signal and the second intermediate signal; and summing the first intermediate signal and the second intermediate signal to obtain the predistorted input signal.

19 . The signal processing circuit arrangement of claim 16 , wherein the first DPD circuit is configured to extrapolate from the lookup table coefficients of the first 2D lookup table of the one or more first 2D lookup tables to obtain the first intermediate signal by:
generating a lookup table output from each of the one or more first 2D lookup tables to obtain one or more lookup table outputs; identifying one or more samples of the first input signal and the second input signal; evaluating one or more functions of the one or more samples to obtain one or

Assignees

• Intel Corp

Inventors

• Molina Albert
• Azadet Kameran

Classifications

• G06F30/36

  Circuit design at the analogue level · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F30/00

  Computer-aided design [CAD] · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• H04L25/03343

  Arrangements at the transmitter end · CPC title