Digital Frontend System for a Radio Transmitter and a Method Thereof

Patent metadata

Field	Value
Publication number	US-2016308559-A1
Application number	US-201615097805-A
Country	US
Kind code	A1
Filing date	Apr 13, 2016
Priority date	Apr 16, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

The present disclosure relates to a digital frontend system for a radio device comprising a digital filter arranged for receiving digital quadrature signals and for filtering the digital quadrature signals and for outputting filtered quadrature signals; a conversion circuit arranged for receiving the filtered quadrature signals and for performing a rectangular to polar conversion of the filtered quadrature signals and for outputting a plurality of polar signals, characterized in that, the plurality of polar signals comprising an amplitude signal and quadrature phase signals.

First claim

1 . A digital frontend system for a radio device comprising:
a digital filter arranged for receiving digital quadrature signals and for filtering the digital quadrature signals and for outputting filtered quadrature signals; and a conversion circuit arranged for receiving the filtered quadrature signals and for performing a rectangular to polar conversion of the filtered quadrature signals and for outputting a plurality of polar signals, wherein the plurality of polar signals comprises an amplitude signal and quadrature phase signals.

2 . The digital frontend system for a radio device as in claim 1 , wherein the conversion circuit comprises a vectoring-mode CORDIC processor and a rotation-mode CORDIC processor, wherein each CORDIC processor comprises two computational columns.

3 . The digital frontend system for a radio device as in claim 2 , wherein the vectoring-mode CORDIC processor is arranged for receiving the filtered quadrature signals, and, for outputting the amplitude signal and a signal indicating a direction of rotation.

4 . The digital frontend system for a radio device as in claim 2 , wherein the rotation-mode CORDIC processor is arranged for rotating a unit vector signal controlled by a signal indicating a direction of rotation, and, for outputting the quadrature phase signals.

5 . The digital frontend system for a radio device as in claim 2 , wherein each computation column of each CORDIC processor comprises a plurality of computational circuits connected in series via a latch logic gate, wherein each computation circuit is arranged to borrow computation time up to a maximum of a half cycle of a clock signal.

6 . The digital frontend system for a radio device as in claim 5 , wherein the latch logic gates form a data pipeline, each latch logic gate being arranged for receiving the clock signal for activating its operation and wherein each subsequent latch logic gate is being activated at an opposite signal level of the clock signal.

7 . The digital frontend system for a radio device as in claim 1 , further comprising a sampling circuit connected at the input of the digital filter and arranged for sampling the digital quadrature signals with an oversampling factor of 4 or more.

8 . The digital frontend system for a radio device as in claim 1 , wherein the digital filter comprises a set of first order FIR filters and a set of second-order FIR filters.

9 . The digital frontend system for a radio device as in claim 1 , further comprising a pre-distortion circuit arranged for pre-distorting the amplitude signal and the quadrature phase signals, and for outputting pre-distorted amplitude signal and pre-distorted quadrature phase signals.

10 . A method for a digital frontend system for a radio device comprising the steps of:
filtering digital quadrature signals and providing filtered digital quadrature signals, and converting the filtered digital quadrature signals into a plurality of polar signals, wherein the plurality of polar signals comprises an amplitude signal and quadrature phase signals.

11 . The method for a digital frontend system for a radio device as in claim 10 , wherein the filtering is performed using a set of carry-save addition operations followed by a vector-merging operation.

12 . The method for a digital frontend system for a radio device as in claim 10 , wherein the conversion is performed iteratively, wherein the computation of each iteration is arranged to borrow computation time up to a maximum of a half cycle of a clock signal.

13 . A radio device comprising an analog front-end system and a digital frontend system as in claim 1 , wherein the analog front-end system comprises a set of digital-to-analog converters arranged for converting digital quadrature phase signals into analog quadrature phase signals.

14 . The radio device as in claim 13 , further comprising a set of second order analog low-pass filters each arranged for filtering one of the analog quadrature phase signals.

15 . A communication network comprising a radio device as in claim 13 .

Assignees

• Imec Vzw
• Univ Leuven Kath

Inventors

• Li Chunshu
• Huang Yanxiang
• Bourdoux André

Classifications

• H04B1/04 Primary

  Circuits · CPC title

• H04B2001/0491

  with frequency synthesizers, frequency converters or modulators · CPC title

• H04B1/0007

  wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage · CPC title

• H03F1/3241

  using predistortion circuits (H03F1/3211, H03F1/3217 take precedence) · CPC title

• H04B2001/0425

  with linearisation using predistortion · CPC title