Control circuit, control method and flyback converter of primary-side feedback control thereof

US2016308447A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016308447-A1
Application numberUS-201615099876-A
CountryUS
Kind codeA1
Filing dateApr 15, 2016
Priority dateApr 16, 2015
Publication dateOct 20, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The disclosure relates to a control circuit, a control method and a flyback converter of primary-side feedback control including the control circuit. On the basis of the current sampling signal feedback, the flyback converter of primary-side feedback control is controlled to operate in a constant on time mode when the input voltage is large, and is controlled to operate in a peak current mode when the input voltage is close to a valley. Thus, the peak value of the primary-side current may not become too small because of a decreased input voltage, further avoiding occurrence of an error sampling after a blanking time due to excessive variations in demagnetization time.

First claim

Opening claim text (preview).

What is claimed is: 1 . A control circuit for controlling a power stage circuit in a flyback converter of primary-side feedback control, comprising: a current sampling circuit configured to sample a primary-side current and to obtain a current sampling signal; a voltage sampling circuit configured to sample a voltage across an auxiliary winding after a blanking time and to obtain a voltage sampling signal; and a control signal generating circuit configured to generate a switching control signal in accordance with said voltage sampling signal and said current sampling signal, in which said switching control signal is generated in a constant on time mode when said current sampling signal is larger than a current threshold at a constant on time point, and is generated in a peak current mode when said current sampling signal is smaller than said current threshold at said constant on time point, wherein said switching control signal controls a power switch in said power stage circuit, and said constant on time point is a time point at which said switching control signal maintains to be valid for a predetermined constant on time period. 2 . The control circuit according to claim 1 , wherein said control signal generating circuit comprises: a set signal generating circuit configured to provide a set signal in accordance with said voltage sampling signal when a secondary-side current crosses zero or a voltage sampling signal is located at a valley; a reset signal generating circuit configured to provide a reset signal when said switching control signal maintains to be valid for said predetermined constant on time period and said current sampling signal rises to reach said current threshold; and a logic circuit configured to set said switching control signal to be valid in accordance with said set signal, and to set said switching control signal to be invalid in accordance with said reset signal. 3 . The control circuit according to claim 2 , wherein said reset signal generating circuit comprises: a timing circuit configured to generate a timing signal which indicates that said switching control signal maintains to be valid for said predetermined constant on time period; a comparator configured to compare said current sampling signal with said current threshold and to provide a comparison result; and a reset logic circuit configured to generate said reset signal in accordance with said timing signal and said comparison result. 4 . The control circuit according to claim 1 , wherein said blanking time varies with a peak value of said current sampling signal. 5 . The control circuit according to claim 4 , wherein said voltage sampling circuit comprises: a blanking circuit configured to provide a blanking signal representing a first time when said peak value of said current sampling signal is smaller than a first value, and provide a blanking signal representing a second time when said peak value of said current sampling signal is larger than a second value, and provide a blanking signal representing a third time when said peak value of said current sampling signal is smaller than said second value and larger than said first value, wherein said third time is a function of said peak value; and a sampling circuit configured to sample a voltage in accordance with said blanking signal. 6 . The control circuit according to claim 5 , wherein said blanking circuit comprises: a blanking threshold generating circuit configured to provide a corresponding blanking threshold in accordance with a relationship between said peak of said current sampling signal and said first value and said second value; and a blanking timing circuit configured to provide said blanking signal representing said corresponding blanking time in accordance with said blanking threshold. 7 . A control circuit for controlling a power stage circuit in a flyback converter of primary-side feedback control, comprising: a current sampling circuit configured to sample a primary-side current and to obtain a current sampling signal; a voltage sampling circuit configured to sample an voltage across an auxiliary winding after a blanking time and to obtain a voltage sampling signal, in which said blanking time varies with a peak value of said current sampling signal; and a control signal generating circuit configured to generate a switching control signal having a constant on time period in accordance with said voltage sampling signal; wherein said switching control signal controls a power switch in said power stage circuit. 8 . The control circuit according to claim 7 , wherein said voltage sampling circuit comprises: a blanking circuit configured to provide a blanking signal representing a first time when said peak value of said current sampling signal is smaller than a first value, and provide a blanking signal representing a second time when said peak value of said current sampling signal is larger than a second value, and provide a blanking signal representing a third time when said peak value of said current sampling signal is smaller than said second value and larger than said first value, wherein said third time is a function of said peak value; and a sampling circuit configured to sample a voltage in accordance with said blanking signal. 9 . The control circuit according to claim 8 , wherein said blanking circuit comprises: a blanking threshold generating circuit configured to provide a corresponding blanking threshold in accordance with a relationship between said peak value of said current sampling signal and said first value and said second value; and a blanking timing circuit configured to provide said blanking signal representing said corresponding blanking time in accordance with said blanking threshold. 10 . A flyback converter of primary-side feedback control, comprising: a power stage circuit; and a control circuit according to claim 1 . 11 . A control method for controlling a flyback converter of primary-side feedback control, comprising: sampling a primary-side current to obtain a current sampling signal, and sampling a voltage across an auxiliary winding after a blanking time to obtain a voltage sampling signal; controlling a power switch in said flyback converter of primary-side feedback control in accordance with said voltage sampling signal and said current sampling signal, wherein said power switch is controlled in a constant on time mode when said current sampling signal is larger than a current threshold at a constant on time point, and is controlled in a peak current mode when said current sampling signal is smaller than said current threshold at said constant on time point; and said constant on time point is a time point at which said switching control signal maintains to be valid for a predetermined constant on time period. 12 . The control method according to claim 11 , wherein said step of controlling a power switch in said flyback converter of primary-side feedback control in accordance with said voltage sampling signal and said current sampling signal comprises: controlling said power switch to be turned on in accordance with said voltage sampling signal when a secondary-side current crosses zero or a voltage sampling signal is located at a valley; and controlling said power switch to be turned off when said switching control signal maintains to be valid for said predetermined constant on time period and said current sampling signal rises to reach said current threshold. 13 . The control method according to claim 11 , wherein said blanking time varies with a peak of said current sampling signal.

Assignees

Inventors

Classifications

  • H02M3/24Primary

    by static converters · CPC title

  • Magnetic structures combining different functions, e.g. storage, filtering or transformation · CPC title

  • the disturbance parameters being input voltage fluctuations · CPC title

  • with galvanic isolation between input and output of both the power stage and the feedback loop · CPC title

  • using a single converter stage both for correction of AC input power factor and generation of a regulated and galvanically isolated DC output voltage (H02M1/4241 takes precedence) · CPC title

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What does patent US2016308447A1 cover?
The disclosure relates to a control circuit, a control method and a flyback converter of primary-side feedback control including the control circuit. On the basis of the current sampling signal feedback, the flyback converter of primary-side feedback control is controlled to operate in a constant on time mode when the input voltage is large, and is controlled to operate in a peak current mode w…
Who is the assignee on this patent?
Silergy Semiconductor Technology Hangzhou Ltd
What technology area does this patent fall under?
Primary CPC classification H02M3/24. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 20 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).