Micro device with stabilization post

Patent metadata

Field	Value
Publication number	US-2016308103-A1
Application number	US-201615192936-A
Country	US
Kind code	A1
Filing date	Jun 24, 2016
Priority date	Jul 8, 2013
Publication date	Oct 20, 2016
Grant date	—

Abstract

A method and structure for stabilizing an array of micro devices is disclosed. A stabilization layer includes an array of stabilization cavities and array of stabilization posts. Each stabilization cavity includes sidewalls surrounding a stabilization post. The array of micro devices is on the array of stabilization posts. Each micro device in the array of micro devices includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

First claim

What is claimed is:

1 . A structure comprising:
a stabilization layer comprising an array of stabilization cavities and an array of stabilization posts, wherein each stabilization cavity includes a stabilization post and sidewalls that surround and are taller than the stabilization post; and an array of chips on the array of stabilization posts; wherein each chip in the array of chips includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface, and each chip includes circuitry to control one or more LED devices.

2 . The structure of claim 1 , wherein the circuitry of each chip is to control more than one LED device.

3 . The structure of claim 2 , wherein each chip includes an active silicon layer and a build up layer underneath the active silicon layer.

4 . The structure of claim 1 , further comprising a sacrificial layer between the stabilization layer and the array of chips, wherein the array of stabilization posts extend through a thickness of the sacrificial layer, and wherein the sacrificial layer spans along a side surface of each of the chips in the array of chips, the side surface running between a top surface and the bottom surface of each chip in the array.

5 . The structure of claim 4 , wherein the sacrificial layer comprises an oxide or nitride.

6 . The structure of claim 1 , further comprising an array of bottom conductive contacts on the bottom surfaces of the array of chips.

7 . The structure of claim 6 , wherein each stabilization post includes a top surface contact area that is less than a bottom surface contact area of a corresponding bottom conductive contact.

8 . The structure of claim 6 , wherein each bottom conductive contact comprises a layer stack.

9 . The structure of claim 8 , wherein the layer stack comprises:
an electrode layer; a mirror layer on the electrode layer; a barrier layer on the mirror layer; a diffusion barrier layer on the barrier layer; and a bonding layer on the diffusion barrier layer;

10 . The structure of claim 8 , wherein the layer stack comprises:
an electrode layer comprising nickel; a mirror layer comprising silver on the electrode layer; a barrier layer comprising titanium on the mirror layer; a diffusion barrier layer comprising platinum on the barrier layer; and a bonding layer comprising a noble metal on the diffusion barrier layer;

11 . The structure of claim 8 , wherein the layer stack comprises a bonding layer, and the bonding layer comprises a noble metal.

12 . The structure of claim 11 , wherein the stabilization layer is formed of a thermoset material.

13 . The structure of claim 12 , wherein the thermoset material comprises benzocyclobutene (BCB), and the noble metal is gold.

14 . The structure of claim 8 , wherein the layer stack further comprises:
an electrode layer on the bottom surface of the chip; and a diffusion barrier layer on and around sidewalls the electrode layer; wherein the bonding layer is on the diffusion barrier layer.

15 . The structure of claim 14 , wherein the stabilization layer is formed of a thermoset material, and the bonding layer comprises a noble metal.

16 . The structure of claim 1 , wherein the stabilization posts in the array of stabilization posts are separated by a pitch of 1 μm to 100 μm.

17 . The structure of claim 1 , wherein each chip includes a top surface that is above a corresponding staging cavity sidewalls top surface.

18 . The structure of claim 1 , wherein each chip has a maximum dimension of 1 μm to 100 μm.

Assignees

• Apple Inc

Inventors

• Hu Hsin-Hua
• Chang Kevin K C
• Bibl Andreas

Classifications

• H10W72/07307

  the auxiliary member being a temporary substrate, e.g. a removable substrate · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/0711

  Apparatus therefor · CPC title

• H10W72/0198 Primary

  batch processes · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title