Solid state photomultiplier with improved pulse shape readout

Patent metadata

Field	Value
Publication number	US-2016308074-A1
Application number	US-201514688008-A
Country	US
Kind code	A1
Filing date	Apr 16, 2015
Priority date	Sep 22, 2014
Publication date	Oct 20, 2016
Grant date	—

Abstract

Embodiments of a solid state photomultiplier are provided herein. In some embodiments, a solid state photomultiplier may include a plurality of pixels, wherein each pixel of the plurality of pixels comprises a plurality of subpixels; and a first set of buffer amplifiers, wherein each buffer amplifier of the first set of buffer amplifiers is respectively coupled to a subpixel of the plurality of subpixels.

First claim

1 . A solid state photomultiplier, comprising:
a plurality of pixels, wherein each pixel of the plurality of pixels comprises a plurality of subpixels; and a first set of buffer amplifiers, wherein each buffer amplifier of the first set of buffer amplifiers is respectively coupled to a subpixel of the plurality of subpixels.

2 . The solid state photomultiplier of claim 1 , wherein the buffer amplifiers are integrally formed with the subpixels.

3 . The solid state photomultiplier of claim 1 , wherein each of the buffer amplifiers are coupled to one another in parallel to form a single output.

4 . The solid state photomultiplier of claim 1 , wherein the first set of buffer amplifiers comprise a plurality of groups of buffer amplifiers, wherein each group of buffer amplifiers are coupled to a respective secondary buffer amplifier of a plurality of secondary buffer amplifiers.

5 . The solid state photomultiplier of claim 4 , wherein the plurality of secondary buffer amplifiers are coupled to a tertiary buffer amplifier.

6 . The solid state photomultiplier of claim 5 , wherein the tertiary buffer amplifier is coupled to readout electronics.

7 . The solid state photomultiplier of claim 4 , wherein the plurality of secondary buffer amplifiers are coupled to readout electronics.

8 . A silicon photomultiplier array, comprising:
a plurality of subpixels arranged in groups to form a pixel; a plurality of buffer amplifiers respectively coupled to the plurality of subpixels; and a plurality of secondary buffer amplifiers, wherein each group of subpixels is coupled to a secondary buffer amplifier of the plurality of secondary buffer amplifiers.

9 . The silicon photomultiplier array of claim 8 , wherein the buffer amplifiers are integrally formed with the subpixels.

10 . The silicon photomultiplier array of claim 8 , wherein each buffer amplifier of the plurality of buffer amplifiers are coupled to one another in parallel to form a single output.

11 . The silicon photomultiplier array of claim 8 , wherein the plurality of secondary buffer amplifiers are coupled to a tertiary buffer amplifier.

12 . The silicon photomultiplier array of claim 8 , wherein the plurality of secondary buffer amplifiers are coupled to readout electronics.

13 . The silicon photomultiplier array of claim 8 , wherein the tertiary buffer amplifier is coupled to readout electronics.

14 . A method for monitoring a solid state photomultiplier, comprising:
monitoring a parameter of a plurality of subpixels of a solid state photomultiplier, wherein the plurality of subpixels are arranged in groups to form a pixel, and wherein each subpixel has a buffer amplifier coupled thereto; determining whether an adjustment of at least one of a V bias or gain of the buffer amplifier of the subpixel is needed; and providing a signal to the buffer amplifier to adjust at least one of the V bias or gain of the buffer amplifier.

15 . The method of claim 14 , wherein the parameter comprises at least one of a temperature, V bias or gain of the subpixel.

16 . The method of claim 14 , wherein adjusting at least one of the V bias or gain of the buffer amplifier comprises adjusting the gain of the buffer amplifier such that the buffer amplifiers of the plurality of subpixels have a substantially uniform gain.

17 . The method of claim 14 , wherein adjusting at least one of the V bias or gain of the buffer amplifier comprises adjusting the V bias at the input of the buffer amplifier while maintaining the gain of the SPPM subpixel with buffer amplifier at a constant.

18 . The method of claim 14 , wherein adjusting at least one of the V bias or gain of the buffer amplifier comprises adjusting the gain of the buffer amplifier while maintaining the V bias at a constant.

Assignees

• Gen Electric

Inventors

• Dolinsky Sergei Ivanovich
• Guo Jianjun
• Mcdaniel David Leo
• Manjeshwar Ravindra Mohan
• Fu Geng

Classifications

• G01T1/247 Primary

  Detector read-out circuitry (for processing gain or off-set correction H04N) · CPC title

• H01L31/10

  Electricity · mapped topic

• H01L31/02027 Primary

  Electricity · mapped topic