Apparatus and Method for a Low Loss Coupling Capacitor

Patent metadata

Field	Value
Publication number	US-2016308073-A1
Application number	US-201514687549-A
Country	US
Kind code	A1
Filing date	Apr 15, 2015
Priority date	Apr 15, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

First claim

1 . A circuit structure for a coupling capacitor comprising:
a p-doped semiconductor substrate (Psub); a deep n-doped semiconductor well (DNW) in the Psub; a p-doped semiconductor well (P well) in the DNW; a first block of a p-doped semiconductor material extending from a surface of the P well into the P well, wherein the first block is a source terminal; a second block of the p-doped semiconductor material extending from the surface of the P well into the P well, wherein the second block is a drain terminal; an insulator block on the P well between the source terminal and the drain terminal; a block of conductor material on the insulator block between the source terminal and the drain terminal, wherein the block of conductor material is a gate; and a metal pattern comprising a plurality of layers of metal lines wherein the layers of metal lines are approximately parallel to the surface, and a plurality of vias through the metal lines and perpendicular to the metal lines, wherein the vias connect the metal lines to the gate, the source terminal, and the drain terminal.

2 . The circuit structure of claim 1 further comprising:
at least one second P well in the DNW;
a third block of the p-doped semiconductor material that serves as a second source terminal, the second source terminal extending from a surface of the second P well into the second P well;
a fourth block of the p-doped semiconductor material that serves as a second drain terminal, the second drain terminal extending from the surface of the second P well into the second P well;
a second insulator block on the second P well between the second source terminal and the second drain terminal; and
a second block of conductor material on the second insulator block that serves as a second gate, the second gate positioned between the second source terminal and the second drain terminal, wherein the vias further connect the metal lines to the second gate, the second source terminal, and the second drain terminal.

3 . The circuit structure of claim 1 , wherein the metal lines are oriented approximately perpendicular to each other in consecutive layers of the metal pattern.

4 . The circuit structure of claim 1 , wherein the metal lines in each layer of the metal pattern are approximately parallel.

5 . The circuit structure of claim 1 , wherein the metal lines in each layer include alternating first lines and second lines, wherein the first lines are connected by the vias to the gate, and wherein the second lines are connected by the vias to the source terminal and the drain terminal.

6 . The circuit structure of claim 1 , wherein the DNW is more heavily doped than the P well.

7 . The circuit structure of claim 1 , wherein opposite end sidewalls of the gate are adjacent to sidewalls of the source terminal and the drain terminal.

8 . The circuit structure of claim 1 , wherein the metal lines in different layers of the metal pattern have different dimensions including at least one of different spacing, different width, different depth, and different length.

9 . The circuit structure of claim 1 , wherein the metal lines in higher layers of the metal pattern from the surface have greater width and larger spacing than the metal lines in lower metal layers.

10 . The circuit structure of claim 1 , wherein the gate and the source terminal and drain terminals are connected to direct current (DC) biases, the Psub is grounded, and the DNW is connected to a power supply through a resistor.

11 . The circuit structure of claim 1 , wherein the circuit structure further comprises:
a p doped semiconductor substrate (Psub); an n-doped semiconductor well (N well) in the Psub; a first block of an n-doped semiconductor material extending from a surface of the N well into the N well, wherein the first block of an n-doped semiconductor material is a second source terminal; a second block of the n-doped semiconductor material extending from the surface of the N well into the N well, wherein the second block of an n-doped semiconductor material is a second drain terminal; a second insulator block on the N well between the second source terminal and the second drain terminal; a second block of conductor material on the second insulator block between the second source terminal and the second drain terminal, wherein the second block of conductor material is a second gate; and wherein the vias further connect the metal lines to the second gate, the second source terminal, and the second drain terminal.

12 . The circuit structure of claim 11 further comprising:
at least one second N well in the Psub;
a third block of the n-doped semiconductor material that serves as a third source terminal, the third source terminal extending from a surface of the second N well into the second N well;
a fourth block of the doped semiconductor material that serves as a third drain terminal, the third drain terminal extending from the surface of the second N well into the second N well;
a third insulator block on the second N well between the third source terminal and the third drain terminal; and
a third block of conductor material that serves as a third gate, the third gate positioned on the surface of the second N well between the third source terminal and the third drain terminal, wherein the vias further connect the metal lines to the third gate, the third source terminal, and the third drain terminal.

13 . The circuit structure of claim 11 , wherein the metal lines are oriented approximately perpendicular to each other in consecutive layers of the metal pattern.

14 . The circuit structure of claim 11 , wherein the metal lines in each layer of the metal pattern are approximately parallel.

15 . The circuit structure of claim 11 , wherein the metal lines in each layer include alternating first lines and second lines, wherein the first lines are connected by the vias to the gate, and wherein the second lines are connected by the vias to the source terminal and the drain terminal.

16 . The circuit structure of claim 11 , wherein the metal lines in different layers of the metal pattern have different dimensions including at least one of different spacing, different width, different depth, and different length.

17 . The circuit structure of claim 11 , wherein the metal lines in higher layers of the metal pattern from the surface have greater width and larger spacing than the metal lines in lower metal layers.

18 . The circuit structure of claim 11 , wherein the second gate, and the second source and second drain terminals are connected to direct current (DC) biases, and wherein the Psub is grounded.

19 - 20 . (canceled)

21 . The method of claim 27 further comprising:
inserting additional vias perpendicular to the metal lines and connecting the metal lines in one layer in the plurality of layers to the metal lines in another layer in the plurality of layers.

22 . The method of claim 27 further comprising:
connecting the gate and the source and drain terminals to direct current (DC) biases;
connecting the Psub to ground; and
connecting the DNW to a power supply through a resistor between the power supply and the DNW.

23 - 24 . (canceled)

25 . The method of claim 29 further comprising:
inserting additional vias perpendicular to the metal lines and connecting the metal lines in one layer in the plurality of layers to the metal lines in another layer on the plurality of layers.

Assignees

• Futurewei Technologies Inc

Inventors

• Creed Brian
• Connell Lawrence
• Jaeger Kent
• Miller Matthew Richard

Classifications

• H10D1/64 Primary

  Variable-capacitance diodes, e.g. varactors · CPC title

• H10D1/048

  having PN junctions, e.g. hybrid capacitors with MOS control · CPC title

• H10D62/393 Primary

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D1/66 Primary

  Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors · CPC title

• H10D84/212

  of only capacitors · CPC title