Method of Forming a Trench Using Epitaxial Lateral Overgrowth

US2016308028A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016308028-A1
Application numberUS-201615187232-A
CountryUS
Kind codeA1
Filing dateJun 20, 2016
Priority dateFeb 6, 2014
Publication dateOct 20, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of forming a trench in a semiconductor material, the method comprising: forming a first dielectric layer on a semiconductor substrate, the first dielectric layer comprising first openings; and growing an epitaxial layer on the semiconductor substrate by an epitaxial lateral overgrowth process, wherein the first openings are filled by the epitaxial layer and the epitaxial layer grows onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer, the gap defining a first trench in the epitaxial layer that extends to the first dielectric layer. 2 . The method of claim 1 , further comprising: forming a second dielectric layer along the opposing sidewalls of the epitaxial layer; and forming a conductive electrode in the first trench such that the first dielectric layer electrically insulates the conductive electrode from the semiconductor substrate and the second dielectric layer electrically insulates the conductive electrode from the epitaxial layer. 3 . The method of claim 2 , further comprising: forming a third dielectric layer over the conductive electrode and over an apex in an outer surface of the epitaxial layer adjacent the first trench; thinning the third dielectric layer to expose the apex and surrounding portions of the epitaxial layer; and etching the epitaxial layer at the exposed apex and surrounding portions of the epitaxial layer to form a second trench in the epitaxial layer spaced apart from the first trench. 4 . The method of claim 1 , wherein forming the first dielectric layer comprises: oxidizing the semiconductor substrate to form a layer of oxide on a first surface of the semiconductor substrate; masking the layer of oxide so that portions of the layer of oxide are unprotected by the mask; etching the unprotected portions of the layer of oxide to the first surface of the semiconductor substrate to form the first dielectric layer with the first openings. 5 . The method of claim 4 , further comprising: re-oxidizing the semiconductor substrate to form oxide regions in the first openings; and etching the oxide regions such that the first openings extend into the semiconductor substrate beyond the first surface. 6 . The method of claim 1 , further comprising: forming second openings in the first dielectric layer after growing the epitaxial layer, the second openings aligned with the gap in the epitaxial layer and extending through the first dielectric layer to the semiconductor substrate so as to expose portions of the semiconductor substrate under the second openings; and etching the exposed portions of the semiconductor substrate under the second openings to form a second trench having opposing sidewalls and a bottom arranged in the semiconductor substrate. 7 . The method of claim 6 , further comprising: removing the epitaxial layer filling the first openings in the first dielectric layer so as to expose portions of the semiconductor substrate under the first openings; and etching the semiconductor substrate under the first openings to form a third trench having opposing sidewalls and a trench bottom arranged in the semiconductor substrate. 8 . The method of claim 7 , wherein the second and third trenches are formed at the same time. 9 . The method of claim 8 , wherein the second and third trenches are formed by a single etching process. 10 . The method of claim 6 , wherein the epitaxial lateral overgrowth process comprises a number of epitaxial cycles, wherein a width of the first openings, a width of the dielectric layer between adjacent ones of the first openings and the number of epitaxial cycles are selected such that an aspect ratio of the second trench is at least 10:1, wherein the aspect ratio is a ratio of a depth of the second trench to a width of the second trench.

Assignees

Inventors

Classifications

  • characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

  • H10P50/642Primary

    Chemical etching · CPC title

  • by chemical means · CPC title

  • using masks for insulating materials · CPC title

  • of the semiconductor materials · CPC title

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What does patent US2016308028A1 cover?
In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacen…
Who is the assignee on this patent?
Infineon Technologies Austria Ag
What technology area does this patent fall under?
Primary CPC classification H10P50/642. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 20 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).