Memory device and electronic device

Patent metadata

Field	Value
Publication number	US-2016307901-A1
Application number	US-201615193189-A
Country	US
Kind code	A1
Filing date	Jun 27, 2016
Priority date	Mar 18, 2011
Publication date	Oct 20, 2016
Grant date	—

Abstract

A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell.

First claim

1 . (canceled)

2 . A semiconductor device comprising:
a first line; a second line; a third line; and a first transistor and a second transistor each including a first gate, a second gate, a source, a drain, and a semiconductor layer, wherein the semiconductor layer of the first transistor is positioned between the first gate of the first transistor and the second gate of the first transistor, wherein the semiconductor layer of the second transistor is positioned between the first gate of the second transistor and the second gate of the second transistor, wherein the first gate of the first transistor is electrically connected to the first line, wherein the second gate of the first transistor is electrically connected to the second line, wherein one of the source and the drain of the first transistor is electrically connected to the third line, wherein one of the source and the drain of the second transistor is electrically connected to the third line, wherein the other of the source and the drain of the first transistor is electrically connected to the second gate of the second transistor, wherein the semiconductor layer of the first transistor includes an oxide semiconductor, wherein the semiconductor layer of the second transistor includes an oxide semiconductor, wherein the first gate of the second transistor overlaps the semiconductor layer of the first transistor, and wherein the semiconductor layer of the second transistor overlaps the other of the source and the drain of the first transistor.

3 . The semiconductor device according to claim 2 , further comprising a fourth line electrically connected to the other of the source and the drain of the second transistor.

4 . The semiconductor device according to claim 2 , wherein a material of the semiconductor layer of the first transistor is the same as a material of the semiconductor layer of the second transistor.

5 . The semiconductor device according to claim 2 , further comprising:
a fourth line; a fifth line; and a third transistor and a fourth transistor each including a first gate, a second gate, a source, a drain, and a semiconductor layer, wherein the semiconductor layer of the third transistor is positioned between the first gate of the third transistor and the second gate of the third transistor, wherein the semiconductor layer of the fourth transistor is positioned between the first gate of the fourth transistor and the second gate of the fourth transistor, wherein the first gate of the third transistor is electrically connected to the first line, wherein the second gate of the third transistor is electrically connected to the fourth line, wherein one of the source and the drain of the third transistor is electrically connected to the fifth line, wherein one of the source and the drain of the fourth transistor is electrically connected to the fifth line, and wherein the other of the source and the drain of the third transistor is electrically connected to the second gate of the fourth transistor.

6 . The semiconductor device according to claim 5 , further comprising a sixth line electrically connected to the other of the source and the drain of the second transistor and the other of the source and the drain of the fourth transistor.

7 . A semiconductor device comprising:
a first line; a second line; a third line; and a first transistor and a second transistor each including a first gate, a second gate, a source, a drain, and a semiconductor layer, wherein the semiconductor layer of the first transistor is positioned between the first gate of the first transistor and the second gate of the first transistor, wherein the semiconductor layer of the second transistor is positioned between the first gate of the second transistor and the second gate of the second transistor, wherein the first gate of the first transistor is electrically connected to the first line, wherein the second gate of the first transistor is electrically connected to the second line, wherein one of the source and the drain of the first transistor is electrically connected to the third line, wherein one of the source and the drain of the second transistor is electrically connected to the third line and the first gate of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to the second gate of the second transistor, wherein the semiconductor layer of the first transistor includes an oxide semiconductor, wherein the semiconductor layer of the second transistor includes an oxide semiconductor, wherein the first gate of the second transistor overlaps the semiconductor layer of the first transistor, and wherein the semiconductor layer of the second transistor overlaps the other of the source and the drain of the first transistor.

8 . The semiconductor device according to claim 7 , further comprising a fourth line electrically connected to the other of the source and the drain of the second transistor.

9 . The semiconductor device according to claim 7 , wherein a material of the semiconductor layer of the first transistor is the same as a material of the semiconductor layer of the second transistor.

10 . The semiconductor device according to claim 7 , further comprising:
a fourth line; a fifth line; and a third transistor and a fourth transistor each including a first gate, a second gate, a source, a drain, and a semiconductor layer, wherein the semiconductor layer of the third transistor is positioned between the first gate of the third transistor and the second gate of the third transistor, wherein the semiconductor layer of the fourth transistor is positioned between the first gate of the fourth transistor and the second gate of the fourth transistor, wherein the first gate of the third transistor is electrically connected to the first line, wherein the second gate of the third transistor is electrically connected to the fourth line, wherein one of the source and the drain of the third transistor is electrically connected to the fifth line, wherein one of the source and the drain of the fourth transistor is electrically connected to the fifth line and the first gate of the fourth transistor, and wherein the other of the source and the drain of the third transistor is electrically connected to the second gate of the fourth transistor.

11 . The semiconductor device according to claim 10 , further comprising a sixth line electrically connected to the other of the source and the drain of the second transistor and the other of the source and the drain of the fourth transistor.

12 . A semiconductor device comprising:
a first line; a second line different from the first line; a first transistor including a first gate, a second gate, a source, a drain, and a semiconductor layer; and a second transistor including a first gate, a source, a drain, and a semiconductor layer, wherein the semiconductor layer of the first transistor is positioned between the first gate of the first transistor and the second gate of the first transistor, wherein the first gate of the first transistor is electrically connected to the first line, wherein the second gate of the first transistor is electrically connected to one of the source and the drain of the second transistor, wherein the first gate of the second transistor is electrically connected to the second line, wherein the first gate of the first transistor overlaps the semiconductor layer of the second transistor, wherein the first transistor is positioned over the second transistor, and wherein each of the semiconductor layer of the first transistor and the semi

Assignees

• Semiconductor Energy Lab

Inventors

• Matsubayashi Daisuke

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• G11C11/404 Primary

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title

• G11C11/405

  with three charge-transfer gates, e.g. MOS transistors, per cell · CPC title

• G11C8/10

  Decoders · CPC title

• H10W20/43

  Layouts of interconnections · CPC title