Reverse-conducting semiconductor device

Patent metadata

Field	Value
Publication number	US-2016307888-A1
Application number	US-201615191295-A
Country	US
Kind code	A1
Filing date	Jun 23, 2016
Priority date	Dec 23, 2013
Publication date	Oct 20, 2016
Grant date	—

Abstract

A Reverse-conducting semiconductor device which comprises a freewheeling diode and an insulated gate bipolar transistor on a common wafer, part of which wafer forms a base layer of a first conductivity type with a first doping concentration and a base layer thickness. The insulated gate bipolar transistor comprises a collector side and an emitter side opposite the collector side of the wafer. A cathode layer of a first conductivity type with at least one first region and a anode layer of a second conductivity type with at least one second and pilot region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The Reverse-conducting-IGBT of the present application satisfies a number of specific geometrical rules.

First claim

1 . A Reverse-conducting semiconductor device, which comprises a freewheeling diode and an insulated gate bipolar transistor on a common wafer, part of which wafer forms a base layer of a first conductivity type with a first doping concentration and a base layer thickness, wherein
the insulated gate bipolar transistor comprises a collector side and an emitter side opposite to the collector side of the wafer, wherein the base layer thickness is the maximum vertical distance between the collector and emitter side of that part of the wafer with the first doping concentration, a cathode layer of the first conductivity type and higher doping concentration than the first doping concentration, and a anode layer of a second conductivity type, which is different from the first conductivity type, are alternately arranged on the collector side, wherein a plurality of source regions of the first conductivity type, a well layer of the second conductivity type and a gate electrode having an electrically conductive gate layer, which is insulated from any layer of the first or second conductivity type by a first insulating layer, are arranged on the emitter side, wherein the cathode layer comprises at least one first region, wherein each first region has a first region width, wherein the anode layer comprises at least one second region, wherein each second region has a second region width, and at least one pilot region, wherein each pilot region has a pilot region width, wherein any region has a region width and a region area, which is surrounded by a region border, wherein a shortest distance is the minimum length between a point within said region area and a point on said region border, each region width is defined as two times the maximum value of all shortest distances within said region, the reverse-conducting semiconductor device comprises an active region in a central part of the device, which active region is an area within the wafer, which includes and is arranged in projection of the source region, well layer and gate layer, wherein each pilot region area is an area having a width of at least two times the base layer thickness, wherein the pilot region is laterally surrounded on the pilot region border by first regions, which have a distance from each other of less than two times the base layer thickness, wherein the at least one second region is that part of the anode layer, which is not the at least one pilot region, wherein a mixed region comprises the at least one first and second regions, wherein the at least one pilot region is arranged in the central part of the device such that the mixed region laterally surrounds the at least one pilot region, wherein the mixed region has a width of at least once the base layer thickness, wherein the total area of the at least one pilot region is between 10% and 45% of the area of the mixed region, wherein each first region width is smaller than the base layer thickness, in each area on the emitter side, which lies in projection to one of the at least one pilot region, the plurality of source regions have a first area density, wherein in each area on the emitter side, which lies in projection to the mixed region, the plurality of source regions have a second area density, wherein the first area density is lower than the second area density.

2 . The Reverse-conducting semiconductor device according to claim 1 , wherein the first area density is at most 50% of the second area density.

3 . The Reverse-conducting semiconductor device according to claim 1 , wherein the first area density is zero.

4 . The Reverse-conducting semiconductor device according to claim 1 , wherein
a gate pad for an external contact of the gate electrode is arranged on the emitter side overlapping a projection to one of the at least one pilot region.

5 . The Reverse-conducting semiconductor device according to claim 1 , wherein at least one or each second region width is larger than the base layer thickness.

6 . The Reverse-conducting semiconductor device according to claim 1 , wherein each pilot region area has a width of at least 2.5 times the base layer thickness.

7 . The Reverse-conducting semiconductor device according to claim 1 , wherein the pilot region has a square, rectangular, circular, star, diamond or hexagon shape.

8 . The Reverse-conducting semiconductor device according to claim 7 , wherein the pilot region has one of a star shape with three protrusions forming a tri-star, four protrusions forming a cross or five or more protrusions.

9 . The Reverse-conducting semiconductor device according to claim 1 , wherein the at least one pilot region is connected to at least one or each second region.

10 . The Reverse-conducting semiconductor device according to claim 9 , wherein the at least one pilot region is one of a single pilot region or at least two pilot regions are interconnected to each other via second regions and wherein the single pilot region or the at least two pilot regions are connected to second regions, which extend to the border of the active region.

11 . The Reverse-conducting semiconductor device according to claim 1 , wherein the total area of the first regions to the area of the second region plus pilot region is between 10% and 45%.

12 . The Reverse-conducting semiconductor device according to claim 1 , wherein the total area of the at least one pilot region is between 18% and 33% of the mixed region.

13 . The Reverse-conducting semiconductor device according to claim 1 , wherein the at least one pilot region consists of one of a single region or the at least one pilot region comprises a plurality of regions which are separated from each other by at most twice the base layer thickness.

14 . The Reverse-conducting semiconductor device according to claim 1 , wherein the mixed region has a width of at least twice the base layer thickness.

15 . The Reverse-conducting semiconductor device according to claim 1 , wherein the gate electrode is formed as one of a trench gate electrode or a planar gate electrode.

16 . The Reverse-conducting semiconductor device according to claim 13 , wherein
the at least one pilot region comprises a plurality of regions which are separated from each other by at most once the base layer thickness.

17 . The Reverse-conducting semiconductor device according to claim 2 , wherein the total area of the first region to the area of the second region plus pilot region is between 10% and 45%.

18 . The Reverse-conducting semiconductor device according to claim 1 , wherein each pilot region area has a width of between 3 and 4 times the base layer thickness.

19 . The Reverse-conducting semiconductor device according to claim, wherein the first area density is at most 10% of the second area density.

20 . The Reverse conducting semiconductor device according to 1 , wherein the total area of the at least one pilot region is between 22 and 28% of the mixed region.

Assignees

• Abb Schweiz Ag

Inventors

• Storasta Liutauras
• Corvasce Chiara
• Le-Gallo Manuel
• Rahimo Munaf

Classifications

• H10D12/481

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D12/032

  of vertical IGBTs · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D64/23

  Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes · CPC title

• H10D62/177

  Base regions of bipolar transistors, e.g. BJTs or IGBTs · CPC title