Method of fabricating semiconductor device having a resistor structure

Patent metadata

Field	Value
Publication number	US-2016307887-A1
Application number	US-201615196781-A
Country	US
Kind code	A1
Filing date	Jun 29, 2016
Priority date	Jul 16, 2014
Publication date	Oct 20, 2016
Grant date	—

Abstract

Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element.

First claim

What is claimed is:

1 . A semiconductor device comprising:
dummy gate structures on a substrate; and a resistor structure on the dummy gate structures, the resistor structure vertically overlapping with at least one of the dummy gate structures.

2 . The semiconductor device of claim 1 , wherein the dummy gate structures extend in a first direction and the resistor structure extends in a second direction crossing the first direction.

3 . The semiconductor device of claim 1 , wherein the resistor structure comprises a resistor element and an etch-retard pattern stacked sequentially on the dummy gate structures.

4 . The semiconductor device of claim 3 , wherein the resistor element comprises a metal.

5 . The semiconductor device of claim 3 , further comprising:
an interlayer insulating layer covering the resistor structure; and a resistor contact structure passing through the etch-retard pattern to contact the resistor element.

6 . The semiconductor device of claim 5 , wherein the resistor contact structure extends into the resistor element.

7 . The semiconductor device of claim 3 , further comprising:
an interlayer insulating layer covering the resistor structure; and at least one pair of resistor contact structures passing through the etch-retard pattern to contact the resistor element.

8 . The semiconductor device of claim 1 , wherein the resistor structure comprises a buffer insulating pattern, a resistor element, and an etch-retard pattern stacked sequentially on the dummy gate structures.

9 . The semiconductor device of claim 8 , wherein the buffer insulating pattern and the etch-retard pattern comprise different materials from each other.

10 . The semiconductor device of claim 8 , wherein the buffer insulating pattern includes oxide and the etch-retard pattern includes nitride.

11 . A semiconductor device comprising:
a substrate including a transistor area and a resistor area; active gate structures on the transistor area of the substrate; dummy gate structures on the resistor area of the substrate; a resistor structure on the dummy gate structures, the resistor structure comprising a buffer insulating pattern, a resistor element, and an etch-retard pattern stacked sequentially on the dummy gate structures; an interlayer insulating layer covering the active gate structures on the transistor area and covering the resistor structure on the resistor area; and at least one pair of resistor contact structures passing through the etch-retard pattern to contact the resistor element.

12 . The semiconductor device of claim 11 , wherein the active gate structures and the dummy gate structures extend in a first direction, and
the resistor structure extends in a second direction crossing the first direction, the resistor structure vertically overlapping with at least one of the dummy gate structures.

13 . The semiconductor device of claim 11 , wherein a side surface of the buffer insulating pattern, a side surface of the resistor element, and a side surface of the etch-retard pattern are aligned along a straight line.

14 . The semiconductor device of claim 11 , wherein the buffer insulating pattern includes silicon oxide and the etch-retard pattern includes silicon nitride.

15 . The semiconductor device of claim 11 , wherein the resistor element comprises a metal.

16 . The semiconductor device of claim 11 , wherein the at least one pair of resistor contact structures extends into the resistor element.

17 . A semiconductor device comprising:
a substrate including a transistor area and a resistor area; gate structures on the resistor area of the substrate; and a resistor on the gate structures, the resistor comprising a resistor element, an etch-retard pattern on the resistor element, and a resistor contact structure passing through the etch-retard pattern to contact the resistor element, wherein the resistor contact structure comprises a core pattern and a barrier pattern surrounding the core pattern.

18 . The semiconductor device of claim 17 , wherein the barrier pattern is in direct contact with the etch-retard pattern.

19 . The semiconductor device of claim 17 , wherein the resistor comprises TiN.

20 . The semiconductor device of claim 17 , wherein the resistor further comprises a buffer insulating pattern interposed between the gate structures and the resistor element and spaced apart from the etch-retard pattern, wherein the buffer insulating pattern includes oxide and the etch-retard pattern includes nitride.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Hyun-Seung
• Jun Hwi-Chan

Classifications

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title