GATE INPUT PROTECTON FOR DEVICES AND SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS

Patent metadata

Field	Value
Publication number	US-2016307886-A1
Application number	US-201615131309-A
Country	US
Kind code	A1
Filing date	Apr 18, 2016
Priority date	Apr 16, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

An integrated gate protection device P for a GaN power transistor D 1 provides negative ESD spike protection. Protection device P comprises a smaller gate width w g enhancement mode GaN transistor Pm. The source of Pm is connected to its gate, the drain of Pm is connected to the gate input of D 1 , and the source of Pm is connected to the intrinsic source of D 1 . When the gate input voltage is taken negative below the threshold voltage for reverse conduction, Pm conducts and quenches negative voltage spikes. When device P comprises a plurality of GaN protection transistors P 1 to Pn, connected in series, it turns on when the gate input voltage applied to the drain of P 1 goes negative by more than the sum of the threshold voltages of P 1 to Pn. The combined gate width of P 1 to Pn is selected to limit the gate voltage excursion of D 1.

First claim

1 . A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative ESD spike protection,
the GaN power transistor D 1 comprising an enhancement mode GaN power transistor of gate width Wg;
the integrated gate protection device P comprising a GaN protection transistor Pm comprising an enhancement mode GaN transistor of smaller gate width w g ,
the gate of the GaN protection transistor Pm being connected to the source of the GaN protection transistor Pm, the drain of the GaN protection transistor Pm being connected to the gate input of the first GaN transistor, and the source of the GaN protection transistor Pm being connected to the intrinsic source of the GaN power transistor D 1 ;
wherein, the GaN protection device P being is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of the GaN protection transistor Pm is taken negative by more than the threshold voltage for reverse conduction of GaN protection transistor Pm, the protection device P conducts.

2 . A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative ESD spike protection,
the GaN power transistor D 1 comprising an enhancement mode GaN power transistor of gate width Wg;
the protection device P comprising first and second GaN protection transistors P 1 and P 2 , each having its gate connected to its source,
the first and second GaN protection transistors being connected in series as a stack, with the source of the first GaN protection transistor P 1 being connected to the drain of the second GaN protection transistor P 2 ; the drain of the first GaN protection transistor P 1 being connected to the gate input of the GaN power transistor, and the source of the second GaN protection transistor P 2 being connected to the intrinsic source of the GaN power transistor D 1 ;
wherein, the GaN protection transistors P 1 and P 2 are normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of P 1 is taken negative voltage for reverse conduction by more than the sum of the threshold voltages of the first and second GaN protection transistors P 1 and P 2 , the protection device P conducts.

3 . A GaN power switching device comprising a GaN power transistor and an integrated gate protection device for negative ESD spike protection,
the GaN power transistor comprising an enhancement mode GaN power transistor of gate width Wg; the integrated gate protection device comprising a plurality n GaN protection transistors P 1 , P 2 , . . . Pn, each comprising an enhancement mode GaN transistor of smaller gate width w g , the gate of each GaN protection transistor P 1 , P 2 , . . . Pn being connected to its source; the n GaN protection transistors being connected in series as a stack, for i=1 to n−1, the source of the ith GaN protection transistor being connected to the drain of the i+1th GaN protection transistor, the drain of the first GaN protection transistor P 1 being connected to the gate input of the GaN power transistor D 1 , the source of the nth GaN protection transistor Pn being connected to the intrinsic source of the GaN power transistor D 1 ; the gate width of the protection device being the sum of the gate width w g of each of the n GaN protection transistors; the effective threshold voltage of the protection device comprising the stack of n GaN protection transistors being the sum of the threshold voltages for reverse conduction of each the n GaN protection transistors, wherein, the GaN protection device P is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of P 1 is taken negative by more than the effective threshold voltage, the GaN protection device P conducts.

4 . The device of claim 3 , wherein the number n of GaN protection transistors is selected to provide an effective threshold voltage of −3V or less.

5 . The device of claim 3 wherein the gate width of the protection device P is selected to limit the gate voltage excursion of the GaN power transistor D 1 to maintain the gate voltage above −10V.

6 . The device of claim 3 further comprising a resistor between the gate input of D 1 and the connection to the drain of P 1 .

7 . The device of claim 3 , wherein the number n of GaN protection transistors is selected to provide an effective threshold voltage of −3V or less and wherein the gate width of the protection device P is selected to limit the gate voltage excursion of the GaN power transistor D 1 to maintain the gate voltage above −10V.

8 . The device of claim 3 , wherein the number n of GaN protection transistors is selected to provide an effective threshold voltage of −3V or less, wherein the gate width of the protection device P is selected to limit the gate voltage excursion of the GaN power transistor D 1 to maintain the gate voltage above −10V, and further comprising a resistor between the gate input of D 1 and the connection to the drain of P 1 .

9 . A GaN power switching device comprising a GaN power transistor and an integrated gate protection device for positive spike ESD protection,
the GaN power transistor comprising an enhancement mode GaN power transistor of gate width Wg; the integrated gate protection device P comprising a plurality n GaN protection transistors P 1 , P 2 , . . . Pn, each comprising an enhancement mode GaN transistor of smaller gate width Wg, the gate of each GaN protection transistor P 1 , P 2 , . . . Pn being connected to its drain; the n GaN protection transistors being connected in series as a stack, for i=1 to n−1, the source of the ith GaN protection transistor being connected to the drain of the i+1th GaN protection transistor, the drain of the first GaN protection transistor P 1 being connected to the gate input of the GaN power transistor D 1 , the source of the nth GaN protection transistor Pn being connected to the intrinsic source of the GaN power transistor D 1 ; the gate width of the protection device being the sum of the gate width w g of each of the n GaN protection transistors; the effective threshold voltage of the protection device comprising the stack of n GaN protection transistors being the sum of the threshold voltages for conduction of each the n GaN protection transistors, wherein the GaN protection device P is normally off, and when the gate the input voltage of the GaN power transistor D 1 applied to the drain of P 1 is taken positive by more than the effective threshold voltage, the GaN protection device P conducts.

10 . The device of claim 9 , wherein the number n of GaN protection transistors P 1 to Pn is selected to provide an effective threshold voltage of at least 8V.

11 . The device of claim 9 , wherein the gate width of the protection device P is selected to limit the peak gate voltage excursion of the GaN power transistor D 1 to between 10V and 16V.

12 . The device of claim 9 , wherein the number n of GaN protection transistors P 1 to Pn is selected to provide an effective threshold voltage of at least 8V, and wherein the gate width of the protection device P is selected to limit the peak gate voltage excursion of the GaN power transistor D 1 to between 10V and 16V.

13 . The GaN power switching device of claim 1 , further comprising a voltage divider connected between the drain and the source of the protection transistor Pm for controlling the gate voltage to the protection transistor Pm at which the protection transistor Pm turns on, the voltage divider dividing the input voltage in a required ratio such that the prot

Assignees

• Gan Systems Inc

Inventors

• Roberts John
• Lafontaine Hugues

Classifications

• H10D89/60 Primary

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H01L29/2003

  Electricity · mapped topic

• H01L27/0266 Primary

  Electricity · mapped topic

• H01L29/778

  Electricity · mapped topic