Memory device layout, semiconductor device, and method of manufacturing memory device

Patent metadata

Field	Value
Publication number	US-2016307882-A1
Application number	US-201514688321-A
Country	US
Kind code	A1
Filing date	Apr 16, 2015
Priority date	Apr 16, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

A layout of a memory device is stored on a non-transitory computer-readable medium. The layout includes a plurality of active area regions, a lowermost interconnect layer, a plurality of memory cells, and a word line. The lowermost interconnect layer includes a first conductive layer over the plurality of active area regions, and a second conductive layer over the first conductive layer. The plurality of memory cells includes the plurality of active area regions. The word line is in the second conductive layer, and is coupled to the plurality of memory cells.

First claim

1 . A layout of a memory device, the layout stored on a non-transitory computer-readable medium and comprising:
a plurality of active area regions; a lowermost interconnect layer, comprising:
a first conductive layer over the plurality of active area regions, and
a second conductive layer over the first conductive layer;
a plurality of memory cells comprising the plurality of active area regions; and a word line in the second conductive layer, the word line coupled to the plurality of memory cells.

2 . The layout of claim 1 , wherein
the word line extends continuously across the plurality of memory cells.

3 . The layout of claim 1 , further comprising:
a dielectric layer interposed between the first conductive layer and the second conductive layer in a first region of the lowermost interconnect layer, wherein the dielectric layer is absent between the first conductive layer and the second conductive layer in a second region of the lowermost interconnect layer, and the first conductive layer is coupled to the second conductive layer in the second region of the lowermost interconnect layer.

4 . The layout of claim 1 , wherein
the plurality of memory cells comprises a plurality of storage nodes in the first conductive layer, the word line in the second conductive layer extends over the plurality of storage nodes in the first conductive layer, and the layout further comprises a dielectric layer interposed between the word line and the plurality of storage nodes.

5 . The layout of claim 4 , wherein
the first conductive layer further comprises, in addition to the plurality of storage nodes, first conductive patterns over the plurality of active area regions, the second conductive layer further comprises, in addition to the word line, second conductive patterns over and coupled to the corresponding first conductive patterns.

6 . The layout of claim 5 , further comprising:
a plurality of bit lines extending over and coupled to the corresponding second conductive patterns.

7 . The layout of claim 1 , further comprising:
a gate electrode over and across the plurality of active area regions, the gate electrode extending along, without overlapping, the word line.

8 . The layout of claim 7 , further comprising:
a lowermost via layer over the lowermost interconnect layer; and a gate contact over the gate electrode, wherein the lowermost via layer comprises a via over both the word line and the gate contact, the via coupling the word line to the gate contact.

9 . The layout of claim 8 , wherein
the word line extends over the gate contact, and the layout further comprises a dielectric layer interposed between the word line and the gate contact.

10 . A semiconductor device, comprising:
a substrate; a gate electrode over the substrate; a first conductive layer over the substrate, the first conductive layer comprising a gate contact over and coupled to the gate electrode; a dielectric layer over the first conductive layer; a second conductive layer over the dielectric layer, the second conductive layer comprising a conductive pattern over the gate contact; and a via over both the conductive pattern and the gate contact, the via coupling the conductive pattern to the gate contact.

11 . The semiconductor device of claim 10 , further comprising:
a plurality of memory cells, wherein the conductive pattern in the second conductive layer comprises a word line coupled to the plurality of memory cells.

12 . The semiconductor device of claim 11 , wherein
a memory cell among the plurality of memory cells comprises the gate electrode, and the via and the gate contact couple the gate electrode of the memory cell to the word line.

13 . The semiconductor device of claim 12 , wherein
the plurality of memory cells comprises a plurality of storage nodes in the first conductive layer, the word line in the second conductive layer extends over the plurality of storage nodes in the first conductive layer, and the dielectric layer is interposed between the word line and the plurality of storage nodes.

14 . The semiconductor device of claim 13 , wherein
the plurality of memory cells further comprises a plurality of active area regions over the substrate, the first conductive layer further comprises, in addition to the plurality of storage nodes and the gate contact, first conductive patterns over the plurality of active area regions, and the second conductive layer further comprises, in addition to the word line, second conductive patterns over and coupled to the corresponding first conductive patterns, without the dielectric layer interposed between the second conductive patterns over and the corresponding first conductive patterns.

15 . The semiconductor device of claim 10 , wherein the via comprises:
an upper portion over and in contact with an upper surface of the conductive pattern in the second conductive layer, and a lower portion continuous to the upper portion, the lower portion over and in contact with an upper surface of the gate contact in the first conductive layer.

16 . The semiconductor device of claim 10 , wherein the via comprises a portion at least partially co-elevational with the conductive pattern in the second conductive layer, said portion in contact with a side face of the conductive pattern.

17 . The semiconductor device of claim 15 , further comprising:
a first inter-layer dielectric (ILD) layer over the substrate, wherein the gate electrode and the first conductive layer are arranged in the first ILD layer; a second ILD layer over the first ILD layer, wherein the second conductive layer and the lower portion of the via is arranged in the second ILD layer; and a third ILD layer over the second ILD layer, wherein the upper portion of the via is arranged in the third ILD layer.

18 - 20 . (canceled)

21 . A semiconductor device, comprising:
a gate electrode over a substrate; a first conductive layer over the substrate, the first conductive layer comprising a gate contact coupled to the gate electrode; a dielectric layer over the first conductive layer; a second conductive layer over the dielectric layer, the second conductive layer comprising a conductive pattern over the gate contact; and a via over the conductive pattern, the via arranged to couple the conductive pattern to the gate contact; and a plurality of memory cells, wherein the conductive pattern comprises a word line coupled to the plurality of memory cells.

22 . The semiconductor device of claim 21 , wherein the via comprises:
a first portion in contact with and over an upper surface of the conductive pattern in the second conductive layer, and a second portion in contact with and over an upper surface of the gate contact in the first conductive layer.

23 . The semiconductor device of claim 22 , further comprising:
a first inter-layer dielectric (ILD) layer over the substrate, wherein the gate electrode and the first conductive layer are within the first ILD layer; a second ILD layer over the first ILD layer, wherein the second conductive layer and the lower portion of the via are within the second ILD layer; and a third ILD layer over the second ILD layer, wherein the upper portion of the via is positioned in the third ILD layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Jui-Lin
• Chang Feng-Ming
• Huang Huai-Ying
• Wang Ping-Wei

Classifications

• H10D89/10 Primary

  Integrated device layouts · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H01L27/1052

  Electricity · mapped topic

• H01L27/0207 Primary

  Electricity · mapped topic

• H10B10/12

  comprising a MOSFET load element · CPC title