Bonding pad arrangment design for semiconductor package

Patent metadata

Field	Value
Publication number	US-2016307873-A1
Application number	US-201615006386-A
Country	US
Kind code	A1
Filing date	Jan 26, 2016
Priority date	Apr 16, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

A semiconductor memory package is provided. The package includes a semiconductor die having a first die portion and a second die portion. A post-passivation layer is on the semiconductor die. A first post-passivation interconnect (PPI) structure includes pluralities of first and second pads arranged in first and second tiers, respectively. The first and second pads are disposed on a first die portion of the semiconductor die. A second PPI structure includes pluralities of third and fourth pads arranged in third and fourth tiers, respectively. The third and fourth pads are disposed on a second die portion of the semiconductor die. One of the first pads and one of the fourth pads are coupled to each other by a first bonding wire. One of the second pads and one of the third pads are coupled to each other.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a semiconductor die having a first die portion, a second die portion, and a scribe line portion between the first and second die portions; a post-passivation layer on the semiconductor die and having a first region and a second region adjacent thereto; a first post-passivation interconnect structure, comprising:
a plurality of first pads arranged in a first tier and a plurality of second pads arranged in a second tier, wherein the first and second pads are disposed on the first region of the post-passivation layer corresponding to the first die portion;
a second post-passivation interconnect structure, comprising:
a plurality of third pads arranged in a third tier and a plurality of fourth pads arranged in a fourth tier, wherein the third and fourth pads are disposed on the first region of the post-passivation layer corresponding to the second die portion;
a first bonding wire having two terminals respectively coupled to one of the first pads and one of the fourth pads; and a second bonding wire having two terminals respectively coupled to one of the second pads and one of the third pads.

2 . The semiconductor package as claimed in claim 1 , wherein the first, second, third and fourth tiers are parallel to each other.

3 . The semiconductor package as claimed in claim 2 , wherein the first, second, third and fourth tiers are parallel to an extending direction of the scribe line portion.

4 . The semiconductor package as claimed in claim 2 , wherein the first tier is parallel to an edge of the first die portion, and the first tier is closer to the edge the first

5 . The semiconductor package as claimed in claim 4 , wherein the second tier is closer to the scribe line portion than the first tier is.

6 . The semiconductor package as claimed in claim 2 , wherein the fourth tier is parallel to an edge of the second die portion, and the fourth tier is closer to the edge the second die portion than the third tier is.

7 . The semiconductor package as claimed in claim 6 , wherein the third tier is closer to the scribe line portion than the fourth tier.

8 . The semiconductor package as claimed in claim 1 , wherein the total number of the first pads is equal to the total number of the fourth pads, and the total number of the second pads is equal to the total number of the third pads.

9 . The semiconductor package as claimed in claim 1 , wherein the first bonding wire has a wire bonding height greater than that of the second bonding wire.

10 . The semiconductor package as claimed in claim 1 , wherein the second post-passivation interconnect structure further comprises a plurality of fifth pads disposed on the second region of the post-passivation layer corresponding to the second die portion and electrically connected to the third and fourth pads.

11 . The semiconductor package as claimed in claim 10 , wherein the fifth pads are arranged along a direction perpendicular to the first, second, third and fourth tiers.

12 . The semiconductor package as claimed in claim 1 , wherein the semiconductor die is a random access memory die.

13 . The semiconductor package as claimed in claim 1 , further comprising:
a first substrate, wherein the semiconductor die is mounted on the first substrate; a second substrate disposed under the first substrate; and a second semiconductor die interposed between the first and second substrates.

14 . The semiconductor package as claimed in claim 13 , wherein the semiconductor memory die is electrically connected to the second semiconductor die through the first substrate.

15 . The semiconductor memory package as claimed in claim 13 , wherein the second semiconductor die is electrically connected to the second substrate.

16 . The semiconductor memory package as claimed in claim 13 , wherein the semiconductor die is misaligned with second semiconductor die, so that a portion of the semiconductor die overhangs the second semiconductor die.

17 . The semiconductor memory package as claimed in claim 13 , wherein the semiconductor die is misaligned with first substrate, so that a portion of the

Assignees

• Mediatek Inc

Inventors

• Chen Ying-Chih
• Chou Che-Ya
• Lin Min-Yu
• Yang Chia-Hao
• Chu Wen-Pin

Classifications

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/07554

  changes in dispositions · CPC title