Method for controlling surface charge on wafer surface in semiconductor fabrication

Patent metadata

Field	Value
Publication number	US-2016307757-A1
Application number	US-201514688191-A
Country	US
Kind code	A1
Filing date	Apr 16, 2015
Priority date	Apr 16, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

A method for processing a semiconductor wafer is provided. The method includes performing a discharging process over the semiconductor wafer in a discharging chamber which is enclosed. The method further includes processing the semiconductor wafer by use of a first processing module after the discharging process. During the discharging process, charged particles applied on the semiconductor wafer are tuned based on the characteristics of the surface of the semiconductor wafer.

First claim

1 . A method for processing at least one semiconductor wafer, comprising:
moving the semiconductor wafer into a discharging chamber; enclosing the discharging chamber to produce an enclosed discharging chamber; detecting at least one characteristic of a surface of the semiconductor wafer in the enclosed discharging chamber; discharging charged particles over the semiconductor wafer in the enclosed discharging chamber, wherein the supply of the charged particles is controlled according to a detected result of the at least one characteristic of the surface of the semiconductor wafer; removing the semiconductor wafer from the discharging chamber; and processing the semiconductor wafer in a processing module.

2 . The method as claimed in claim 1 , further comprising transferring the semiconductor wafer and passing it through an ambient controlled environment in an interface module before the semiconductor wafer being transferred into the discharging chamber.

3 . The method as claimed in claim 1 , wherein detecting at least one characteristic of a surface of the semiconductor wafer is performed at a single point of the surface of the semiconductor wafer.

4 . The method as claimed in claim 1 , wherein detecting at least one characteristic of a surface of the semiconductor wafer is performed by scanning a region of the surface of the semiconductor wafer.

5 . The method as claimed in claim 1 , wherein the semiconductor wafer is transferred into the discharging chamber via a first door of the discharging chamber and is removed from the discharging chamber via a second door of the discharging chamber, wherein the second door is different from the first door.

6 . The method as claimed in claim 1 , further comprising purging gas over the discharging chamber after the semiconductor wafer is removed from the discharging chamber or before another semiconductor wafer is transferred into the discharging chamber.

7 . The method as claimed in claim 1 , wherein the semiconductor wafer is transferred from a carrier, which is configured to contain a plurality of semiconductor wafers, via the discharging chamber for a discharging process and is sent to the processing module.

8 . The method as claimed in claim 1 , wherein the semiconductor wafer is transferred from the processing module via the discharging chamber for a discharging process and is sent to a carrier which is configured to contain a plurality of semiconductor wafers.

9 . A method for processing at least one semiconductor wafer, comprising:
performing a discharging process over the semiconductor wafer in a discharging chamber which is enclosed, wherein during the discharging process, charged particles applied on the semiconductor wafer are tuned based on at least one characteristic of a surface of the semiconductor wafer; and processing the semiconductor wafer by use of a first processing module after the discharging process.

10 . The method as claimed in claim 9 , further comprising:
performing a post discharging process in the discharging chamber or another discharging chamber which is enclosed after the semiconductor wafer has been processed by the first processing module; and processing the semiconductor wafer which has been processed in the post discharging process by use of a second processing module.

11 . The method as claimed in claim 10 , further comprising:
moving the semiconductor wafer which has been processed in the post discharging process to a carrier; and transferring the semiconductor wafer to the second processing module via the carrier.

12 . The method as claimed in claim 9 , further comprising:
moving the semiconductor wafer from a carrier to the discharging chamber; enclosing the discharging chamber for performing the discharging process; moving the semiconductor wafer from the discharging module to the carrier or another carrier; and transferring the semiconductor wafer which has been processed in the discharging process to the first processing module via the carrier or the other carrier.

13 . The method as claimed in claim 9 , further comprising performing a gas purge during an time interval between operations of performing the discharging process over two different semiconductor wafers.

14 . The method as claimed in claim 9 , wherein charged particles are tuned based on at least one characteristic of a single point on the surface of the semiconductor wafer.

15 . The method as claimed in claim 9 , wherein charged particles are tuned based on at least one characteristic of a region on the surface of the semiconductor wafer.

16 - 20 . (Canceled)

21 . The method as claimed in claim 1 , wherein an air environment held in the enclosed discharging chamber is secluded from an outside of the enclosed discharging chamber.

22 . The method as claimed in claim 6 , wherein purging gas over the discharging chamber is performed when the discharging chamber is sealed.

23 . The method as claimed in claim 9 , wherein when the discharging chamber is enclosed, an air environment held in the discharging chamber is secluded from an outside of the discharging chamber.

24 . The method as claimed in claim 9 , further comprising passing the semiconductor wafer through an ambient controlled environment in an interface module before entering and leaving the discharging chamber.

25 . The method as claimed in claim 13 , wherein the gas purge is performed when the discharging chamber is sealed.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Weibo
• Chuang Jui-Ping
• Lu Chen-Hsiang
• Ku Shao-Yen

Classifications

• H10P72/3222

  Loading to or unloading from a conveyor · CPC title

• H10P72/3221

  Overhead conveying · CPC title

• H10P74/207 Primary

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P72/0468

  comprising a chamber adapted to a particular process · CPC title