A computing device for iterative appilcation of table networks

Patent metadata

Field	Value
Publication number	US-2016306973-A1
Application number	US-201415100647-A
Country	US
Kind code	A1
Filing date	Nov 19, 2014
Priority date	Dec 5, 2013
Publication date	Oct 20, 2016
Grant date	—

Abstract

A computing device ( 500 ) comprising an electronic storage ( 510 ) and an electronic processor ( 550 ) coupled to the storage, the storage storing a series of table networks ( 110 , T 1 , T 2 ), the processor being configured to compute an iterated function on a global data-input ( 121 , w 0 ) and a global state-input ( 121 , s 0 ) by applying table networks of the series of table networks, —a table network ( 112, 114 , T i ) of the series being configured for a corresponding data-function (ƒ i ) and state-function (g i ) and is configured to map a data-input ( 121, 122 , s i ) to a data-output ( 122, 123 , w i ) according to the corresponding data-function (ƒ i ), and to simultaneously map a state-input ( 121, 122 , s i-1 ) to a state-output ( 122, 123 , s i ) according to a state-function (g i ), —the electronic processor being configured to iterate applying the series of table networks (T 1 , T 2 , T 1 , T 2 ), a table network (T 1 ) of the iteratively applied table networks to the global data-input (w 0 ) and global state-input (s 0 ), and a successive table network (T 2 , T 1 , T 2 ) of said iteration to the data-output and state-output of a preceding table network of the series, the iterated application of the series determines a global data function (ƒ=ƒ 2 ∘ƒ 1 ∘ƒ 2 ∘ƒ 1 ) on the global data-input and determines a global state function (g=g 2 ∘g 1 ∘g 2 ∘g 1 ) on the global state-input, thus obtaining an intermediate data-output (w inter =f(w 0 )) and an intermediate state-output (s inter =g(s 0 )), —the electronic storage is further storing a protecting table network ( 150 ) configured to cooperate with the series of table networks for countering modifications made to table networks of the series, the protecting table network being configured to receive as input: the intermediate state-output ( 126 , s inter ), and a global state-input ( 131 , s 0 ), the protecting table network being configured to verify that the global state-function (g) applied to the global state-input (s 0 ) produces the intermediate state-output (s inter =g(s 0 )?).

First claim

1 . A computing device comprising an electronic storage and an electronic processor coupled to the storage, the storage storing a series of table networks ( 110 , T 1 , T 2 ), the processor being configured to compute an iterated function on a global data-input ( 121 , w 0 ) and a global state-input ( 121 , s 0 ) by applying table networks of the series of table networks,
a table network ( 112 , 114 , T i ) of the series being configured for a corresponding data-function (ƒ i ) and state-function (g ) and is configured to map a data-input ( 121 , 122 , w i-1 ) to a data-output ( 122 , 123 , w i ) according to the corresponding data-function (ƒ i ), and to simultaneously map a state-input ( 121 , 122 , s i-1 ) to a state-output ( 122 , 123 , s i ) according to a state-function (g i ), the electronic processor being configured to iterate applying the series of table networks (T 1 , T 2 , T 1 , T 2 ), a table network (T 1 ) of the iteratively applied table networks to the global data-input (w 0 ) and global state-input (s 0 ), and a successive table network (T 2 , T 1 , T 2 ) of said iteration to the data-output and state-output of a preceding table network of the series, the iterated application of the series determines a global data function (ƒ=ƒ 2 ∘ƒ 1 ∘ƒ 2 ∘ƒ 1 ) on the global data-input and determines a global state function (g=g 2 ∘g 1 ∘g 2 ∘g 1 ) the global state-input, thus obtaining an intermediate data-output (w inter =ƒ(w 0 )) and an intermediate state-output (s inter =g(s 0 )), the electronic storage is further storing a protecting table network configured to cooperate with the series of table networks for countering modifications made to table networks of the series, the protecting table network being configured to receive as input: the intermediate state-output ( 126 , s inter ), and a global state-input ( 131 , s 0 ), the protecting table network being configured to verify that the global state-function (g) applied to the global state-input (s 0 ) produces the intermediate state-output (s inter =g(s 0 )?).

2 . A computing device as in claim 1 , wherein a single iteration of the table networks of the series (T 1 , T 2 ), determines a single-iteration state function ({tilde over (g)}=g 2 ∘g 1 ) on the global state-input, the single-iteration state function ({tilde over (g)}) being idempotent or nilpotent.

3 . A computing device as in claim 2 , wherein the single-iteration state function ({tilde over (g)}) is the identity, the protecting table network being configured to verify that the global state-input (s 0 ) equals the intermediate state-output (s inter =s 0 ?).

4 . A computing device as in claim 1 , wherein the protecting table network is configured to receive a further input dependent upon the number of iterations of series.

5 . A computing device as in claim 1 , wherein the protecting table network is further configured to receive as input: the intermediate data-output ( 126 , w inter =ƒ(w 0 )) and produce as output a protected data-output (cw) and protected state-output (cs) ( 143 ), wherein
the protected data-output (cw) is equal to the intermediate data-output (ƒ(w)) in case the verification is successful (s inter =g(s 0 )) and the protected data-output (cw) is unequal to the intermediate data-output in case the verification is unsuccessful for at least some values of the global data-input (w 0 ) and the global state-input (s 0 ).

6 . A computing device as in claim 1 , wherein the protecting table network comprises a state table network ( 130 , T c ), the state table network (T c ) being configured for the global state-function (g) and is configured to map the state-input (s 0 ) to a verification state-output ( 132 s c =g(s 0 )), the protecting table network being configured to verify that verification state-output equals the intermediate state-output (s inter =s c ?).

7 . A computing device as in claim 6 , wherein the state table network ( 130 , T c ) comprise fewer tables than the tables networks in series together.

8 . A computing device as in claim 1 , wherein all state-functions (g i ) corresponding to a table network (T i ) in the series are equal (g 0 ).

9 . A computing device as in claim 1 , wherein
the global data-input (w 0 ) and a global state-input (s 0 ) are encoded together into a single global input, the data-input (w i-1 ) and the state-input (s i-1 ) of a table network of the series are encoded together into a single input, the data-output (w i ) and the state-output (s i ) of a table network of the series are encoded together into a single output, the intermediate data-output (w 1 ) and the intermediate state-output (s 2 ) are encoded together into a single intermediate output, the protected data-output (cw) and the protected state-output (cs) are encoded together into a single protected output.

10 . A computing device comprising an electronic storage and an electronic processor coupled to the storage, the storage storing a series of table networks ( 110 , T 1 , T 2 ), the processor being configured to compute a function on a global data-input ( 121 , w 0 ) and a global state-input ( 121 , s c ) by applying table networks of the series of table networks,
a table network ( 112 , 114 , T i ) of the series being configured for a corresponding data-function (ƒ i ) and state-function (g i ) and is configured to map a data-input ( 121 , 122 , w i-1 ) to a data-output ( 122 , 123 , w i ) according to the corresponding data-function (ƒ i ), and to simultaneously map a state-input ( 121 , 122 , s i-1 ) to a state-output ( 122 , 123 , s i ) according to a state-function (g i ), the electronic processor being configured to apply the series of table networks (T 1 ,T 2 ), a table network (T 1 ) of the applied table networks to the global data-input (w 0 ) and global state-input (s c ), and a successive table network (T 2 ) to the data-output and state-output of a preceding table network of the series, the application of the series determines a global data function (ƒ=ƒ 2 ∘ƒ 1 ) on the global data-input and determines a global state function (g=g 2 ∘g 1 ) on the global state-input, thus obtaining an intermediate data-output (w inter =ƒ(w 0 )) and an intermediate state-output (s inter =g(s 0 ), the electronic storage is further storing a protecting table network ( 150 ) configured to cooperate with the series of table networks for countering modifications made to table networks of the series, the protecting table network being configured to receive as input: the intermediate state-output ( 126 , s inter ) and a global state-input ( 131 , s 0 ), the protecting table network being configured to verify that the global state-function (g) applied to the global state-input (s 0 ) produces the intermediate state-output (s inter =g(s 0 )?), wherein the global state function is the identity, or the series comprises more than two table networks to compute the global state-function, and the protecting table network comprises a single state table network ( 130 , T c ), the state table network (T c ) being configured for the global state-function (g) and being configured to map the state-input (s 0 ) to a verification state-output ( 132 s c =g(s 0 )), the protecting table network being configured to verify that verification state-output equals the intermediate state-output (s inter =s c ?), the state table network ( 130 , T c ) comprising fewer tables than the tables networks in series 110 together.

11 . A computing method using a series of table networks ( 110 , T 1 ,T 2 ), the method being configured to compute an iterated function on a global data-input ( 121 , w 0 ) and a global state-input ( 121 , s 0 ) by applying table networks of the series of table networks,
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Assignees

• Koninklijke Philips Nv

Inventors

• Bruekers Alphons Antonius Maria Lambertus
• Gorissen Paulus Mathias Hubertus Mechtildis Antonius
• Tolhuizen Ludovicus Marinus Gerardus Maria
• Schepers Hendrik Jan Jozef Hubertus
• Pestrin Alan
• Deng Mina

Classifications

• G06F2221/033

  Test or assess software · CPC title

• G06F2221/2123

  Dummy operation · CPC title

• G06F21/566 Primary

  Dynamic detection, i.e. detection performed at run-time, e.g. emulation, suspicious activities · CPC title

• G06F21/556

  involving covert channels, i.e. data leakage between processes (inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755) · CPC title

• H04L2209/16

  Obfuscation or hiding, e.g. involving white box · CPC title