System, method and computer-accessible medium for security-centric electronic system design

Patent metadata

Field	Value
Publication number	US-2016306902-A1
Application number	US-201615099826-A
Country	US
Kind code	A1
Filing date	Apr 15, 2016
Priority date	Apr 16, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

An exemplary system, method and computer-accessible medium can be provided which can include, for example, generating a super control dataflow graph(s) (CDFG) by applying a plurality of electronic system level ESL design constraints associated with an integrated circuit, determining an upper bound(s) number and a lower bound(s) number based on a number of CDFGs in the super CDFG(s)—with each number being one metric of a capability of the integrated circuit to resist reverse engineering attack—, and inserting a component(s) into a register transfer level netlist to effectuate a modification of the upper bound(s) and the lower bound(s).

First claim

What is claimed is:

1 . A non-transitory computer-accessible medium having stored thereon computer-executable instructions, wherein, when a computer arrangement executes the instructions, the computer arrangement is configured to perform procedures comprising:
generating at least one super control dataflow graph (CDFG) by applying a plurality of electronic system level ESL design constraints associated with an integrated circuit; determining at least one upper bound number and at least one lower bound number based on a number of CDFGs in the at least one super CDFG; and inserting at least one component into a register transfer level (RTL) netlist to effectuate a modification of the at least one upper bound and the at least one lower bound.

2 . The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to generate the ESL design constraints based on at least one high-level synthesis apparatus.

3 . The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to generate the at least one super CDFG by applying the ESL design constraints to the RTL netlist.

4 . The computer-accessible medium of claim 1 , wherein the RTL netlist description includes a particular netlist description having at least one hidden controller.

5 . The computer-accessible medium of claim 4 , wherein the computer arrangement is further configured to generate the at least one super CDFG based on the particular netlist.

6 . The computer-accessible medium of claim 4 , wherein the computer arrangement is further configured to determine the at least one upper bound and the at least one lower bound based on the particular netlist.

7 . The computer-accessible medium of claim 4 , wherein the computer arrangement is further configured to insert the at least one component into the particular netlist.

8 . The computer-accessible medium of claim 7 , wherein the computer arrangement is further configured to insert at least one component into the RTL netlist such that the integrated circuit is further resilient to at least one reverse engineering attack.

9 . The computer-accessible medium of claim 1 , wherein the at least one upper bound and the at least one lower bound are each at least one metric of a capability of the integrated circuit to resist at least one reverse engineering attack.

10 . The computer-accessible medium of claim 1 , wherein the RTL netlist is a RTL netlist of an integrated circuit which includes at least one datapath and at least one controller part.

11 . The computer-accessible medium of claim 1 , wherein the at least one component includes at least one dummy component.

12 . The computer-accessible medium of claim 11 , wherein the at least one dummy component includes at least one extra state in a finite state machine.

13 . The computer-accessible medium of claim 12 , wherein the at least one extra state is at least one of at least one unused state or at least one state with no outgoing transition.

14 . The computer-accessible medium of claim 13 , wherein the at least one state with no outgoing transition is at least one black-hole state.

15 . The computer-accessible medium of claim 11 , wherein the at least one dummy component includes at least one transition in a finite state machine.

16 . The computer-accessible medium of claim 13 , wherein the at least one transition is at least one invalid transition.

17 . The computer-accessible medium of claim 1 , wherein the at least one super CDFG is a plurality of super CDFGs, and wherein a number of super CDFGs is based on a graph-theoretic formulation.

18 . The computer-accessible medium of claim 17 , wherein:
the at least one super CDFG is a plurality of super CDFGs, the at least one component is a plurality of components, and a number of super CDFGs is based on a product of a number of possible components and a number of possible sets of inputs.

19 . A method comprising:
generating at least one super control dataflow graph (CDFG) by applying a plurality of electronic system level ESL design constraints associated with an integrated circuit; determining at least one upper bound number and at least one lower bound number based on a number of CDFGs in the at least one super CDFG; and inserting at least one component into a register transfer level (RTL) netlist to effectuate a modification of the at least one upper bound and the at least one lower bound.

20 . A system, comprising:
at least one computer hardware arrangement configured to:
generate at least one super control dataflow graph (CDFG) by applying a plurality of electronic system level ESL design constraints associated with an integrated circuit;
determine at least one upper bound number and at least one lower bound number based on a number of CDFGs in the at least one super CDFG; and
insert at least one component into a register transfer level (RTL) netlist to effectuate a modification of the at least one upper bound and the at least one lower bound.

Assignees

• Univ New York

Inventors

• Rajendran Jeyavijayan
• Karri Ramesh
• Sinanoglu Ozgur

Classifications

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F21/79 Primary

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F17/505 Primary

  Physics · mapped topic

• G06F21/566

  Dynamic detection, i.e. detection performed at run-time, e.g. emulation, suspicious activities · CPC title