Method for extending hold time of power supply units

US2016306402A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016306402-A1
Application numberUS-201514687614-A
CountryUS
Kind codeA1
Filing dateApr 15, 2015
Priority dateApr 15, 2015
Publication dateOct 20, 2016
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Various examples of the present technology provide systems and methods for monitoring an AC power to a computing system, generating a power failure signal when the AC power is determined abnormal, and cause one or more components of the computing system to be switched to a low power mode or shut down to reduce power consumption of the computing system. In particular, the various embodiments of the present technology provide a method to extend hold time of a power supply unit (PSU), thus extend power-on time of a server system during an input power interruption.

First claim

Opening claim text (preview).

What is claimed is: 1 . A server system, comprising: at least one processor; a power supply unit (PSU), the PSU including a power-loss-detection circuit configured to monitor a status of an AC input power to the server system and, in response to a determination that the AC input power is abnormal, generate a power failure signal; and a controller, the controller configured to, in response to receiving the power failure signal, cause one or more energy storage devices (ESDs) to support power consumption of at least one of a plurality of components of the server system and cause at least one action to be taken to reduce power consumption of the server system. 2 . The system of claim 1 , wherein the at least one action includes causing power supplied to one or more specific components of the server system to be reduced or disabled. 3 . The system of claim 2 , wherein the one or more specific components of the server system include a CPU, memory, just bunch of disks (JBOD), and one or more cooling devices. 4 . The system of claim 2 , wherein the controller is further configured to: in response to a determination that the AC input power is back to normal, cause the one or more ESDs to be recharged; and cause power supplied to the one or more specific components of the server system to be resumed to a power amount under normal operations. 5 . The system of claim 1 , wherein the at least one action includes facilitating a clock or frequency scaling of a CPU, a system bus or memory of the server system, when at least one of a plurality of predetermined conditions occurs. 6 . The system of claim 5 , wherein the plurality of predetermined conditions include the determination that the AC input power is abnormal, and detecting an over-temperature condition on one or more of the plurality of components of the server system. 7 . The system of claim 5 , wherein the controller is further configured to cause the system to: propagate programmable information stored within an I/O controller of the server system to a clock generator, wherein the programmable information indicates an amount of an operating frequency of a first clock signal to the CPU to be adjusted; and cause the first clock signal to the CPU to be adjusted according to the programmable information. 8 . The system of claim 7 , wherein the controller is further configured to cause the system to: cause a second clock signal to the system bus to be adjusted proportionally to the first clock signal. 9 . The system of claim 7 , wherein the controller is further configured to cause the system to: generate a voltage modification signal to a power supply unit (PSU) of the server system; and cause a CPU core voltage to be adjusted proportionally to an adjusted operating frequency of the CPU. 10 . The system of claim 9 , wherein the controller is further configured to cause the system to: in response to a determination that the input power the AC input power is back to normal, cause the CPU core voltage to be resumed to a voltage amount under normal operations; and cause the operating frequency of the first clock signal to the CPU to be resumed to a frequency amount under normal operations. 11 . The system of claim 5 , wherein the controller is further configured to cause the system to: generate a fan-shut-down signal; and cause one or more cooling devices of the server system to be shut down. 12 . The system of claim 11 , wherein the one or more cooling devices include at least one liquid cooling device or fan. 13 . A computer-implemented method for enhancing memory fault tolerance in a server system, comprising: receiving a power failure signal, the power failure signal indicating an input power to the server system being abnormal; causing one or more energy storage devices (ESDs) to support power consumption of at least one of a plurality of components of the server system; and causing at least one action to be taken to reduce power consumption of the server system. 14 . The computer-implemented method of claim 13 , wherein causing at least one action to be taken includes: facilitating a clock or frequency scaling of a CPU, a system bus or DDR of the server system, when at least one of a plurality of predetermined conditions occurs. 15 . The computer-implemented method of claim 14 , further comprising: propagating programmable information stored within an I/O controller of the server system to a clock generator, wherein the programmable information indicates an amount of an operating frequency of a first clock signal to the CPU to be adjusted; and causing the first clock signal to the CPU to be adjusted according to the programmable information. 16 . The computer-implemented method of claim 15 , further comprising: causing a second clock signal to the system bus to be adjusted proportionally to the first clock signal. 17 . The computer-implemented method of claim 15 , further comprising: generating a voltage modification signal to a power supply unit (PSU) of the server system; and causing a CPU core voltage to be adjusted proportionally to an adjusted operating frequency of the CPU. 18 . A non-transitory computer-readable storage medium including instructions that, when executed by at least one processor of a server system, cause the server system to: monitor a status of an AC input power to the server system; in response to a determination that the AC input power is abnormal, generate a power failure signal; cause one or more energy storage devices (ESDs) to support power consumption of at least one of a plurality of components of the server system; and cause at least one action to be taken to reduce power consumption of the server system. 19 . The non-transitory computer-readable storage medium of claim 18 , wherein the instructions when executed further cause the system to: cause power supplied to one or more specific components of the server system to be reduced or disabled. 20 . The non-transitory computer-readable storage medium of claim 19 , wherein the instructions when executed further cause the system to: in response to a determination that the AC input power is back to normal, cause the one or more ESDs to be recharged; and cause power supplied to the one or more specific components of the server system to be resumed to a power amount under normal operations.

Assignees

Inventors

Classifications

  • G06F1/206Primary

    comprising thermal management · CPC title

  • by switching off individual functional units in the computer system · CPC title

  • by lowering clock frequency · CPC title

  • Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title

  • G06F1/263Primary

    Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2016306402A1 cover?
Various examples of the present technology provide systems and methods for monitoring an AC power to a computing system, generating a power failure signal when the AC power is determined abnormal, and cause one or more components of the computing system to be switched to a low power mode or shut down to reduce power consumption of the computing system. In particular, the various embodiments of …
Who is the assignee on this patent?
Quanta Comp Inc
What technology area does this patent fall under?
Primary CPC classification G06F1/206. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Oct 20 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).