Code examination by scheduler timeline manipulation

Patent metadata

Field	Value
Publication number	US-2016299786-A1
Application number	US-201514684265-A
Country	US
Kind code	A1
Filing date	Apr 10, 2015
Priority date	Apr 10, 2015
Publication date	Oct 13, 2016
Grant date	—

Abstract

A scheduler timeline comprising a sequence of time stamped scheduling activities associated with scheduling execution of a computer program is exposed. The timeline can subsequently be modified in a variety of ways and utilized to schedule activities. For instance, activities can be added, removed, or reordered in a timeline. The timeline can be manipulated to enable code examination including testing and monitoring.

First claim

What is claimed is:

1 . A system comprising:
a processor coupled to a memory, the processor configured to execute the following computer-executable components stored in the memory: a first component configured to expose a first timeline comprising a sequence of time stamped scheduling activities associated with scheduling execution of a computer program; a second component configured to transform the first timeline to second timeline that varies from first timeline; and a third component configured to schedule execution of activities in accordance with the second timeline.

2 . The system of claim 1 , the second timeline includes a checkpoint activity that saves state associated with the computer program.

3 . The system of claim 2 , the second timeline includes failure and recovery activities.

4 . The system of claim 3 further comprises a fourth component configured to provide a result of a comparison between an actual result and an expected result.

5 . The system of claim 1 , the second timeline includes an expanded time interval between at least two of the activities.

6 . The system of claim 1 , the second timeline includes at least one performance monitoring activity.

7 . A method comprising:
employing at least one processor configured to execute computer-executable instructions stored in a memory to perform the following acts: receiving a timeline comprising a sequence of time stamped scheduling activities associated with scheduling execution of a computer program; modifying the timeline; and initiating scheduling with the modified timeline.

8 . The method of claim 7 , modifying the timeline comprises performing virtual time dilation between two contiguous activities to increase a time interval between the contiguous activities.

9 . The method of claim 7 , modifying the timeline comprises adding a checkpoint activity.

10 . The method of claim 9 further comprises performing virtual time dilation to a time interval between two contiguous activities in the timeline and inserting the checkpoint activity between the two contiguous activities.

11 . The method of claim 9 , modifying the timeline comprises adding a recovery activity after the checkpoint activity.

12 . The method of claim 11 further comprises performing virtual time dilation to a time interval between two contiguous activities in the timeline and inserting the recovery activity between the two contiguous activities.

13 . The method of claim 11 , modifying the timeline comprises simulating failure between the checkpoint activity and the recovery activity.

14 . The method of claim 7 further comprises comparing output of scheduling with the modified timeline with expected output to determine if an error exists.

15 . The method of claim 7 , modifying the timeline comprises inserting one or more activities to monitor performance.

16 . A computer-readable storage medium having instructions stored thereon that enable at least one processor to perform a method upon execution of the instructions, the method comprising:
receiving a timeline comprising a sequence of time stamped scheduling activities associated with scheduling execution of a computer program; and checking for non-deterministic scheduling by determining whether the timeline includes one or more activities that are scheduled at the same time.

17 . The computer-readable storage medium of claim 16 , the method further comprises generating a warning if one or more activities are scheduled at the same time.

18 . The computer-readable storage medium of claim 16 , the method further comprises identifying deterministic combinations of one or more activities are scheduled at the same time.

19 . The computer-readable storage medium of claim 16 , the method further comprises performing virtual time dilation to inject an interval of time between one or more activities scheduled at the same time.

20 . The computer-readable storage medium of claim 16 , the method further comprises injecting checkpoint and recovery operations into the timeline.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• De Smet Bart
• Rozell Eric

Classifications

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/5038 Primary

  considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups) · CPC title

• G06F2209/483

  Multiproc · CPC title

• G06F9/4887

  involving deadlines, e.g. rate based, periodic · CPC title