Auto-vectorization in just-in-time compilers for dynamically typed programming languages

US2016299746A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016299746-A1
Application numberUS-201615083157-A
CountryUS
Kind codeA1
Filing dateMar 28, 2016
Priority dateApr 7, 2015
Publication dateOct 13, 2016
Grant date

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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A computing device with an optimizing compiler is disclosed that is configured to generate optimized machine code including a vector operation corresponding to multiple scalar operations where the vector operation is a single operation on multiple pairs of operands. The optimizing compiler includes a vector guard condition generator configured to generate a vector guard condition for one or more vector operations, a mapping module to generate a mapping between elements of the vector guard condition and positions of the relevant scalar operations in the non-optimized machine code or intermediate representation of the source code, and a guard condition handler configured to initiate execution from a particular scalar operation in the non-optimized machine code or intermediate representation if the vector guard condition is triggered. The computing device may include a non-optimizing compiler and/or an interpreter to perform execution of the scalar operations if the vector guard condition is triggered.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method for compiling source code, the method comprising: receiving source code of a dynamically-typed language wherein types of operations are not defined in the source code; generating an intermediate representation of the source code; creating and executing non-optimized machine code that includes multiple scalar operations; determining if the multiple scalar operations are frequently executed so that the non-optimized machine code may be optimized; transforming, if the non-optimized machine code may be optimized, the multiple scalar operations in the intermediate representation from a scalar form to a vector operation, wherein each scalar operation includes a single pair of operands, and the vector operation is single operation on multiple pairs of operands; creating a vector guard condition for, at least, the vector operation; creating optimized machine code that includes the vector operation and the vector guard condition; executing the optimized machine code containing the vector operation; mapping an element of the vector guard condition in the optimized machine code to a particular scalar operation of the non-optimized machine code if the vector guard condition is triggered during execution of the vector operation in the optimized machine code; and executing the non-optimized code from the particular scalar operation if the optimized machine code fails the vector guard condition. 2 . The method of claim 1 , including: comparing a reference vector with an output of the vector operation to determine if the vector guard condition is triggered. 3 . The method of claim 1 , including switching to execute the optimized machine code after executing the non-optimized machine code. 4 . The method of claim 1 , wherein mapping includes generating a mapping table that maps, for the vector guard condition, each of a plurality of element positions of the vector operation to a node in the non-optimized machine code. 5 . A computing device for compiling source code, the device including: a non-optimizing compiler configured to generate non-optimized machine code that includes multiple scalar operations, each scalar operation includes a single pair of operands; an optimizing compiler configured to generate optimized machine code including a vector operation corresponding to the multiple scalar operations, the vector operation is single operation on multiple pairs of operands, the optimizing compiler including: a vector guard condition generator configured to generate a vector guard condition for, at least, the vector operation; a mapping module to generate a mapping between elements of the vector guard condition and positions in the non-optimized machine code; and a guard condition handler configured to initiate execution of a particular scalar operation of the non-optimized machine code if the vector guard condition is triggered. 6 . The computing device of claim 5 , wherein the source code is a type selected from the group consisting of JavaScript, LISP, SELF, Python, Perl, and ActionScript. 7 . A method for compiling source code, the method comprising: receiving source code of a dynamically-typed language wherein types of operations are not defined in the source code; generating an intermediate representation from the source code; performing interpreted execution of the intermediate representation; gathering profile information to determine if optimized machine code should be created or not; transforming multiple scalar operations in the intermediate representation from a scalar form to a vector operation, wherein each scalar operation includes a single pair of operands, and the vector operation is single operation on multiple pairs of operands; creating a vector guard condition for, at least, a vector operation; creating optimized machine code that includes the vector operation and the vector guard condition; executing the optimized machine code containing the vector operation; mapping an element of the vector guard condition in the optimized machine code to a particular scalar operation of the intermediate representation if the vector guard condition is triggered during execution of the vector operation in the optimized machine code; and switching back to start interpretation of the intermediate representation from the particular scalar operation when the guard condition is triggered. 8 . The method of claim 7 , including: generating a reference vector; and comparing the reference vector with an output of the vector operation to determine if the vector guard condition is triggered. 9 . The method of claim 7 , including switching back to execute the optimized machine code after starting the interpretation. 10 . The method of claim 7 , including: generating a mapping table that maps, for the vector guard condition, each of a plurality of element positions of the vector operation to a node in the intermediate representation of the source code. 11 . A computing device for compiling source code, the computing device including: an interpreter configured to interpret an intermediate representation of the source code that includes multiple scalar operations, each scalar operation includes a single pair of operands; an optimizing compiler configured to generate optimized machine code including a vector operation corresponding to the multiple scalar operations, the vector operation is single operation on multiple pairs of operands, the optimizing compiler including: a vector guard condition generator configured to generate a vector guard condition for one or more vector operations; a mapping module to generate a mapping between elements of the vector guard condition and positions in the intermediate representation of the source code; and a guard condition handler configured to initiate interpretation of a particular scalar operation of the intermediate representation of the source code if the vector guard condition is triggered. 12 . The computing device of claim 11 , wherein the source code is a type selected from the group consisting of JavaScript, LISP, SELF, Python, Perl, and ActionScript.

Assignees

Inventors

Classifications

  • Embedded in an application, e.g. JavaScript in a Web browser · CPC title

  • Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators · CPC title

  • Data distribution · CPC title

  • G06F8/41Primary

    Compilation · CPC title

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What does patent US2016299746A1 cover?
A computing device with an optimizing compiler is disclosed that is configured to generate optimized machine code including a vector operation corresponding to multiple scalar operations where the vector operation is a single operation on multiple pairs of operands. The optimizing compiler includes a vector guard condition generator configured to generate a vector guard condition for one or mor…
Who is the assignee on this patent?
Qualcomm Innovation Ct Inc
What technology area does this patent fall under?
Primary CPC classification G06F8/41. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Oct 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).