Cache Operation in a Multi-Threaded Processor

Patent metadata

Field	Value
Publication number	US-2016299700-A1
Application number	US-201514873027-A
Country	US
Kind code	A1
Filing date	Oct 1, 2015
Priority date	Apr 9, 2015
Publication date	Oct 13, 2016
Grant date	—

Abstract

Cache operation in a multi-threaded processor uses a small memory structure referred to as a way enable table that stores an index to an n-way set associative cache. The way enable table includes one entry for each entry in the n-way set associative cache and each entry in the way enable table is arranged to store a thread ID. The thread ID in an entry in the way enable table is the ID of the thread associated with a data item stored in the corresponding entry in the n-way set associative cache. Prior to reading entries from the n-way set associative cache identified by an index parameter, the ways in the cache are selective enabled based on a comparison of the current thread ID and the thread IDs stored in entries in the way enable table which are identified by the same index parameter.

First claim

1 . A multi-threaded processor comprising:
a set associative cache comprising a plurality of cache entries arranged in a plurality of ways, each cache entry comprising a data field and a tag field; a way enable table comprising a plurality of way enable table entries, each way enable table entry corresponding to a cache entry in the set associative cache and comprising a thread ID field arranged to store a thread ID for a thread associated with a data item stored in the data field of the corresponding cache entry; and hardware logic arranged to selectively enable ways in the set associative cache based at least in part on a comparison of a current thread ID and thread IDs stored in way enable table entries in said way enable table identified by an index parameter.

2 . The multi-threaded processor according to claim 1 , further comprising:
hardware logic arranged to read cache entries in enabled ways in the set associative cache which are identified by the index parameter and to compare the tag field in each cache entry which is read to a reference value.

3 . The multi-threaded processor according to claim 2 , wherein the reference value is a program counter.

4 . The multi-threaded processor according to claim 1 , wherein the thread associated with a data item stored in the data field of the corresponding cache entry comprises a current thread ID at a time when the data item was stored in the data field of the corresponding cache entry.

5 . The multi-threaded processor according to claim 1 , wherein the set associative cache is implemented in a first type of memory and the way enable table is implemented in a second type of memory.

6 . The multi-threaded processor according to claim 5 , wherein the set associative cache is a RAM based cache and the way enable table is implemented in registers.

7 . The multi-threaded processor according to claim 1 , wherein an index value identifies one cache entry in each way in the set associative cache and the index value further identifies a subset of the way enable table entries, each way enable table entry in the subset corresponding to one of the identified cache entries.

8 . The multi-threaded processor according to claim 1 , wherein the set associative cache is an instruction cache.

9 . The multi-threaded processor according to claim 1 , wherein the set associative cache is a jump register cache.

10 . The multi-threaded processor according to claim 1 , further comprising:
a second set associative cache comprising a second plurality of cache entries arranged in a second plurality of ways, each cache entry in the second set associative cache comprising a data field and a tag field; a second way enable table comprising a second plurality of way enable table entries, each way enable table entry in the second way enable table corresponding to a cache entry in the second set associative cache and comprising a thread ID field arranged to store a thread ID for a thread associated with a data item stored in the data field of the corresponding cache entry in the second set associative cache; and second hardware logic arranged to selectively enable ways in the second set associative cache based at least in part on a comparison of a current thread ID and thread IDs stored in way enable table entries in the second way enable table identified by a second index parameter.

11 . The multi-threaded processor according to claim 10 , wherein the set associative cache is a jump register cache and the second set associative cache is an instruction cache.

12 . A method of accessing cache entries in a set associative cache in a multi-threaded processor, arranged in a plurality of ways with each cache entry comprising a data field and a tag field, the method comprising:
accessing two or more way enable table entries in a way enable table identified by an index parameter, each way enable table entry corresponding to a cache entry in the set associative cache and comprising a thread ID field arranged to store a thread ID for a thread associated with a data item stored in the data field of the corresponding cache entry; for each accessed way enable table entry, comparing the stored thread ID and a current thread ID; and in response to the comparison identifying a match between the current thread ID and the stored thread ID in a way enable table entry, enabling the way in the set associative cache containing the corresponding cache entry.

13 . The method according to claim 12 , further comprising:
in response to the comparison identifying no match between the current thread ID and the stored thread ID in a way enable table entry, disabling the way in the set associative cache containing the corresponding cache entry.

14 . The method according to claim 12 , further comprising:
reading cache entries in enabled ways in the set associative cache which are identified by the index parameter.

15 . The method according to claim 12 , further comprising:
in response to an update to a cache entry in the set associative cache, updating the thread ID stored in the way enable table entry which corresponds to the updated cache entry.

16 . A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system for generating a representation of an integrated circuit from definitions of circuit elements and data defining rules for combining those circuit elements, cause the computer system to generate the processor as set forth in claim 1 .

17 . A non-transitory computer readable storage medium having encoded thereon computer readable instructions that, when executed at a computer system for generating a representation of an integrated circuit from definitions of circuit elements and data defining rules for combining those circuit elements, cause the computer system to generate a processor configured to:
access two or more way enable table entries in a way enable table identified by an index parameter, each way enable table entry corresponding to a cache entry in a set associative cache, the set associative cache comprising a plurality of cache entries arranged in a plurality of ways and each cache entry comprising a data field and a tag field and each way enable table entry comprising a thread ID field arranged to store a thread ID for a thread associated with a data item stored in the data field of the corresponding cache entry; compare the stored thread ID and a current thread ID for each accessed way enable table entry; and in response to the comparison identifying a match between the current thread ID and the stored thread ID in a way enable table entry, to enable the way in the set associative cache containing the corresponding cache entry.

Assignees

• Imagination Tech Ltd

Inventors

• Day Philip

Classifications

• G06F12/0842 Primary

  for multiprocessing or multitasking · CPC title

• G06F2212/1021

  Hit rate improvement · CPC title

• G06F3/0638

  Organizing or formatting or addressing of data · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F2212/22

  Employing cache memory using specific memory technology · CPC title