Power efficient processor architecture

Patent metadata

Field	Value
Publication number	US-2016299559-A1
Application number	US-201615134770-A
Country	US
Kind code	A1
Filing date	Apr 21, 2016
Priority date	Sep 6, 2011
Publication date	Oct 13, 2016
Grant date	—

Abstract

In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

First claim

1 : A mobile device comprising:
an apparatus; a dynamic random access memory (DRAM) coupled to the apparatus; a data storage, wherein the apparatus comprises:
a cryptographic accelerator;
a video accelerator;
a memory controller; and
a processor comprising:
a first plurality of cores;
a second plurality of cores, wherein the second plurality of cores heterogeneous to and having a lower power consumption than the first plurality of cores;
an interconnect to couple the first plurality of cores and the second plurality of cores and a shared cache memory coupled to at least the first plurality of cores; and
a logic to cause a core of the second plurality of cores to execute an operation, wherein based at least in part on a performance level of the core of the second plurality of cores, the logic is to cause an execution state of the core of the second plurality of cores to be transferred to a core of the first plurality of cores to enable the core of the first plurality of cores to execute the operation.

2 . The mobile device of claim 1 , wherein the logic is to cause the core of the second plurality of cores and not the core of the first plurality of cores to be woken in response to an interrupt when the core of the first plurality of cores and the core of the second plurality of cores are in a low power state.

3 . The mobile device of claim 2 , wherein the logic is to cause the core of the first plurality of cores and not the core of the second plurality of cores to be woken in response to the interrupt when an entry of a table indicates that the core of the second plurality of cores incurred an undefined fault in response to a previous interrupt of the same type as the interrupt.

4 . The mobile device of claim 2 , wherein the logic is to provide a subset of an execution state of the core of the first plurality of cores to the core of the second plurality of cores in response to the interrupt.

5 . The mobile device of claim 4 , wherein in response to a determination that the core of the second plurality of cores cannot handle at least one requested operation, the logic is to obtain the subset of the execution state from the core of the second plurality of cores and to merge the execution state subset with a remainder of the execution state of the core of the first plurality of cores stored in a temporary storage area.

6 . The mobile device of claim 2 , wherein the video accelerator is to perform a task and to send the interrupt to the logic upon completion of the task.

7 . The mobile device of claim 2 , wherein the logic is to analyze a plurality of interrupts and if a majority of the plurality of interrupts are to be handled by the core of the first plurality of cores, the logic is to not wake the core of the second plurality of cores in response to the interrupt and instead wake the core of the first plurality of cores.

8 . The mobile device of claim 1 , wherein the processor comprises a multicore processor, the logic comprising:
a wakeup logic; a state transfer logic; an undefined handling logic; and an interrupt history storage.

9 . The mobile device of claim 1 , further comprising an interrupt controller to receive a plurality of interrupts and direct the plurality of interrupts to one or more cores of at least one of the first plurality of cores and the second plurality of cores.

10 . The mobile device of claim 1 , wherein the mobile device comprises a smartphone.

11 . The mobile device of claim 1 , wherein the mobile device comprises a tablet computer.

12 . The mobile device of claim 1 , further comprising an audio device.

13 . The mobile device of claim 1 , wherein the core of the first plurality of cores further comprises at least one cache memory.

14 . A method comprising:
causing a core of a second plurality of cores of a processor of a mobile device to execute an operation, based at least in part on a performance level of the core of the second plurality of cores, the processor comprising a first plurality of cores, the second plurality of cores heterogeneous to and having a lower power consumption than the first plurality of cores, an interconnect to couple the first plurality of cores and the second plurality of cores and a shared cache memory coupled to at least the first plurality of cores; and causing an execution state of the core of the second plurality of cores to be transferred to a core of the first plurality of cores to enable the core of the first plurality of cores to execute the operation.

15 . The method of claim 14 , further comprising causing the core of the second plurality of cores and not the core of the first plurality of cores to be woken in response to an interrupt when the core of the first plurality of cores and the core of the second plurality of cores are in a low power state.

16 . The method of claim 15 , further comprising causing the core of the first plurality of cores and not the core of the second plurality of cores to be woken in response to the interrupt when an entry of a table indicates that the core of the second plurality of cores incurred an undefined fault in response to a previous interrupt of the same type as the interrupt.

17 . The method of claim 15 , further comprising providing a subset of an execution state of the core of the first plurality of cores to the core of the second plurality of cores in response to the interrupt.

18 . At least one computer readable storage medium comprising instructions that when executed enable a system to:
cause a core of a second plurality of cores of a processor of a mobile device to execute an operation, based at least in part on a performance level of the core of the second plurality of cores, the processor comprising a first plurality of cores, the second plurality of cores heterogeneous to and having a lower power consumption than the first plurality of cores, an interconnect to couple the first plurality of cores and the second plurality of cores and a shared cache memory coupled to at least the first plurality of cores; and cause an execution state of the core of the second plurality of cores to be transferred to a core of the first plurality of cores to enable the core of the first plurality of cores to execute the operation.

19 . The at least one computer readable medium of claim 18 , further comprising instructions that when executed enable the system to cause the core of the second plurality of cores and not the core of the first plurality of cores to be woken in response to an interrupt when the core of the first plurality of cores and the core of the second plurality of cores are in a low power state.

20 . The at least one computer readable medium of claim 19 , further comprising instructions that when executed enable the system to cause the core of the first plurality of cores and not the core of the second plurality of cores to be woken in response to the interrupt when an entry of a table indicates that the core of the second plurality of cores incurred an undefined fault in response to a previous interrupt of the same type as the interrupt.

21 . A system comprising:
a processor comprising:
a first plurality of cores;
a second plurality of cores, a core of the second plurality of cores having a lower power consumption when in operation than a core of the first plurality of cores;
an interconnect coupled to the first plurality of cores and coupled to the second plurality of cores; and
a shared cache memory coupled to at least the first plurality o

Assignees

• Intel Corp

Inventors

• Herdrich Andrew J
• Illikkal Rameshkumar G
• Iyer Ravishankar
• Srinivasan Sadogopan
• Moses Jaideep
• Makineni Srihari

Classifications

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title